Power Trade-Offs and Low-Power in Analog CMOS ICs

2003 ◽  
Keyword(s):  
Low Power ◽  
Analog Cmos ◽  
Trade Offs ◽  
Power Trade

AND-OR-XOR NETWORK SYNTHESIS WITH AREA-POWER TRADE-OFF

2011 ◽  
Vol 20 (06) ◽  
pp. 1019-1035 ◽  
Author(s):  
SAMBHU NATH PRADHAN ◽  
M. TILAK KUMAR ◽  
SANTANU CHATTOPDHYAY
Keyword(s):  
Boolean Function ◽  
Solution Space ◽  
Leakage Power ◽  
Total Power ◽  
Synthesis Process ◽  
Network Synthesis ◽  
Trade Off ◽  
Delay Performance ◽  
Trade Offs ◽  
Power Trade

In this paper, a heuristic based on genetic algorithm to realize multi-output Boolean function as three-level AND-OR-XOR network performing area power trade-off is presented. All the previous works dealt with the minimization of number of product terms only in the two sum-of-product-expressions representing a Boolean function during AND-OR-XOR network synthesis. To the best of knowledge this is the first ever effort to incorporate total power, that is, dynamic and leakage power along with the area (in terms of number of product terms) during three-level AND-OR-XOR networks synthesis. The synthesis process, without changing the delay performance results in lesser number of product terms compared to those reported in the literature. It also enumerates the trade-offs present in the solution space for different weights associated with area, dynamic power, and leakage power of the resulting circuit.

Framework Design Supporting QoS-Power Trade-Offs for Heterogeneous Networked Systems

2008 ◽  
pp. 71-80
Author(s):  
Christos Antonopoulos ◽  
Evangelos Topalis ◽  
Aggeliki Prayati ◽  
Spilios Giannoulis ◽  
Antonis Athanasopoulos ◽  
...  
Keyword(s):  
Networked Systems ◽  
Framework Design ◽  
Trade Offs ◽  
Power Trade

CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

2006 ◽  
Vol 16 (01) ◽  
pp. 193-219 ◽  
Author(s):  
S. DELEONIBUS ◽  
B. de SALVO ◽  
T. ERNST ◽  
O. FAYNOT ◽  
T. POIROUX ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Short Channel Effects ◽  
Short Channel ◽  
Trade Offs ◽  
Future System ◽  
The Future ◽  
Channel Effects

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

Architectural trade-offs in the design of low power FIR filtering cores

2004 ◽  
Vol 151 (1) ◽  
pp. 10 ◽  
Author(s):  
A.T. Erdogan ◽  
E. Zwyssig ◽  
T. Arslan
Keyword(s):  
Low Power ◽  
Trade Offs ◽  
Fir Filtering

Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm

2006 ◽  
Author(s):  
Felix Buergin ◽  
Flavio Carbognani ◽  
Martin Hediger ◽  
Hektor Meier ◽  
Robert Meyer-Piening ◽  
...  
Keyword(s):  
Low Power ◽  
Hearing Aid ◽  
Vlsi Implementation ◽  
Trade Offs

Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm

2006 ◽  
Author(s):  
F. Buergin ◽  
F. Carbognani ◽  
M. Hediger ◽  
H. Meier ◽  
R. Meyer-Piening ◽  
...  
Keyword(s):  
Low Power ◽  
Hearing Aid ◽  
Vlsi Implementation ◽  
Trade Offs

Area-power trade-offs for flexible filtering in green radios

2010 ◽  
Vol 12 (2) ◽  
pp. 158-167 ◽  
Author(s):  
Navin Michael ◽  
Christophe Moy ◽  
Achutavarrier Prasad Vinod ◽  
Jacques Palicot
Keyword(s):  
Trade Offs ◽  
Power Trade
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