scholarly journals Power Optimization of Delay Constrained Circuits

VLSI Design ◽  
2001 ◽  
Vol 12 (2) ◽  
pp. 125-138
Author(s):  
Anshuman Nayak ◽  
Malay Haldar ◽  
Prith Banerjee ◽  
Chunhong Chen ◽  
Majid Sarrafzadeh
Keyword(s):  
Power Dissipation ◽  
Short Circuit ◽  
Average Power ◽  
Accurate Estimate ◽  
Voltage Scaling ◽  
Power Reduction ◽  
Total Power ◽  
Gate Sizing ◽  
Dynamic Power ◽  
Circuit Power

We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS) techniques for power optimizations. We introduce a fast heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the load capacitance of the gates. Our results show that the combination of VS and GS perform better than the techniques applied in isolation. An average power reduction of 73% is obtained when decisions are taken assuming dynamic power only. In contrast, average power reduction is 77% when decisons include the short circuit power dissipation.

Design Methodology for Multipliers with Active Leakage and Dynamic Power Reduction

2012 ◽  
Vol 182-183 ◽  
pp. 1440-1445
Author(s):  
Xi Tian ◽  
Fei Qiao ◽  
Zai Wang Dong ◽  
Yu Jun Liu ◽  
Yu Ting Zhao
Keyword(s):  
Input Signal ◽  
Power Dissipation ◽  
Design Methodology ◽  
Dynamic Range ◽  
Power Reduction ◽  
Total Power ◽  
Power Gating ◽  
Dynamic Power ◽  
On Chip ◽  
Novel Design

A novel design methodology for multipliers to reducing both active leakage and dynamic power using dynamic power gating is presented, where sleep transistors are inserted between the real and virtual ground rails of various parts of the multiplier which could be selectively turned on/off. On-chip sleep signals are generated from one input signal of the multiplier which has larger dynamic range. By detecting the magnitude of the input signal, the idle parts of the multiplier are identified and the power gating schemes are dynamically applied even when the multiplier is performing useful computation. Simulations show that the total power dissipation of the proposed multiplier could be reduced up to 39.3% in a typical DSP application.

A METHODOLOGY FOR THE ESTIMATION OF CAPACITIVE CROSSTALK-INDUCED SHORT-CIRCUIT ENERGY

2007 ◽  
Vol 16 (03) ◽  
pp. 455-465 ◽  
Author(s):  
MOSIN MONDAL ◽  
YEHIA MASSOUD
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Short Circuit ◽  
Average Error ◽  
Dynamic Power ◽  
Characterization Technique ◽  
Circuit Power ◽  
Nanometer Regime

In the nanometer regime, crosstalk significantly impacts the dynamic power consumption of a chip. In this paper, we present a methodology for analyzing crosstalk-induced short-circuit power dissipation in cell-based digital designs. We introduce a new cell pre-characterization technique for facilitating the estimation of crosstalk-induced short-circuit power. Examples demonstrate that the presented methodology is three orders of magnitude faster than circuit simulators while the average error is as low as 3.5%.

A NEW CMOS DRIVER MODEL FOR TRANSIENT ANALYSIS AND POWER DISSIPATION ANALYSIS

1996 ◽  
Vol 07 (02) ◽  
pp. 269-285
Author(s):  
HAIFANG LIAO ◽  
WAYNE WEI-MING DAI ◽  
RUI WANG
Keyword(s):  
Power Dissipation ◽  
Transient Analysis ◽  
Short Circuit ◽  
Computing Time ◽  
Nonlinear Effects ◽  
Short Circuit Current ◽  
Driver Model ◽  
Linear Quadratic ◽  
Piecewise Model ◽  
Circuit Power

While most transient analysis techniques of interconnect networks ignore the nonlinearity of the driving gates, most CMOS driver models do not take into account the distributed loads. In this paper, we propose a new CMOS driver model which can handle distributed-lumped loads for transient analysis and power dissipation analysis. The output current of the CMOS driver is represented by a linear-quadratic-exponential piecewise model, taking into account the slope of the input signal, nonlinear effects of the driver and interconnect effects of the load. The CMOS transient leakage (short-circuit) current, thus short-circuit power dissipation, can be accurately evaluated. The model provides accuracy comparable to that of SPICE3e2 with one or two orders of magnitude less computing time.

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