3D IC packaging technologies are emerging as they are able to respond to the demands for smaller form-factor, faster, high density interconnection at cheaper cost. Moreover, for a 3D IC package, through silicon vias (TSVs) provide high wiring density interconnection, thus improve electrical performance due to shorter interconnection from the chip to the substrate. However, TSV technology is still facing severe challenges as the physical design problems due to the existence of the copper vias remain resolved. Apart from thermal expansion mismatch, the problems are due in part to the nonlinear behavior of SAC lead-free solder used in the package as an echo of environmental concerns and RoHS directive. However, there exists a wide range of values of the parameters of the creep model used to describe the nonlinear behavior of SAC. The effects of the variations of these parameters on the thermal reliability of IC packages, particularly the 3D IC package with built-in TSVs considered herein, is of interest. Presented in the paper is a study on assessment of the influence of the creep parameters of SAC solders on the isothermal fatigue reliability of a 3D IC package with built-in TSVs. The results show that as the strain rate is linear proportional to C1, a larger C1 tends to enlarge the strain rate hence decrease the fatigue life. However, the relationship between the fatigue life of the specific IC package is not linear. Although the variation of C2 causes a large variation in the fatigue life, its effect becomes insignificant when a moderate value of C2 is considered. As a power parameter to the hyperbolic sine function of the creep model, C3 contributes a 40% variation to the fatigue life. Lastly, the fatigue life increases with C4 value, and the gain of fatigue life increases as C4 approaches the upper limit considered herein.
Interfacial Effects During Thermal Cycling of Cu-Filled Through-Silicon Vias (TSV)
