Effect of Thermal Cyclic Loading on Stress-Strain Response and Fatigue Life of 3D Chip Stacking Structure

The thermo-mechanical reliability of IMCs (Ni3Sn4, Cu3Sn, Cu6Sn5) solder joints and Sn-3.9Ag-0.6Cu solder joints was investigated systematically in 3D chip stacking structure subjected to an accelerated thermal cyclic loading based on finite element simulation and Taguchi method. Effects of different control factors, including high temperature, low temperature, dwell time of thermal cyclic loading, and different IMCs on the stress-strain response and fatigue life of solder joints were calculated respectively. The results indicate that maximum stress-strain can be found in the second solder joint on the diagonal of IMC solder joints array; for Sn-3.9Ag-0.6Cu solder joints array, the corner solder joints show the obvious maximum stress-strain, these areas are the crack propagated locations. The stress-strain and fatigue life of solder joints is more sensitive to dwell temperature, especially to high temperature; increasing the high temperature, dwell time, or decreasing the low temperature, can reduce the stress-strain and enlarge the fatigue life of solder joints. Finally, the optimal design in the 3D-IC structure has the combination of the Cu6Sn5/Cu3Sn, 373 K high temperature, 233 K low temperature, and 10 min dwell time. The fatigue lives of Sn-3.9Ag-0.6Cu under 218–398 K loading in the 3D assembly based on the creep strain are 347.4 cycles, which is in good agreement with experimental results (380 cycles).

Towards a Description Synthesis of the Entanglement of the Substrate with the Interconnection Network, for Fast Modeling of 3D RF circuits

3D chip stacking is considered known to overcome conventional 2D-IC issues, using Trough Silicon Via (TSVs) to ensure vertical signal transmission between data. If the electrical behaviour of 3D interconnections (redistribution metal lines and through silicon vias) used in 3D IC stack technologies are to be explored in this paper, the substrate itself is of interest, via Green Kernels by solving Poisson's equation analytically. Using this technique, the substrate coupling and loss in IC's can be analysed. We implement our algorithms in MATLAB. This method has been already used; but, it permits to extract impedances for a stacked uniform layers substrate. We have extended for any numbers of embedded contacts, of any shape. On a second hand, we grasp the background noise between any two points, in the bulk, or at the surface, from a transfer impedance extraction technique. With an analog algorithm, a strength of this work, we calculate unsteady solutions of the heat equation, using a spreading resistance concept. This method has been adapted to stacked layers. With this general tool of impedance field, we investigate on the problems encountered by interconnects, especially the vias, the substrate, and their entanglement. A calculation of thermal mechanical stresses and their effects on substrate crack (max and min stresses), devices (i.e: transistors) and hotspots, are made to track the performance. But, to well understand the interconnection incidence on 3D system performances, it is important to consider the whole electrical context; it seems relevant to consider the possible couplings between vias, not only by the electromagnetic field, but also by any possible energy transfer between interconnects; more generally, one of actual problem is to determine where the energy is really confined in such 3D circuits, before find solutions to limit pollutions coming from electro-magneto -thermal phenomena or background noises.

Effect of Thermal Cyclic Loading on Stress-Strain Response and Fatigue Life of 3D Chip Stacking Structure

In this paper, the thermo-mechanical reliability of IMCs (Ni3Sn4, Cu3Sn, Cu6Sn5) solder joints and Sn-3.9Ag-0.6Cu solder joints were investigated systematically in 3D chip stacking structure subjected to an accelerated thermal cyclic loading based on finite element simulation and Taguchi method. Effects of different control factors, including high temperature, low temperature, dwell time of thermal cyclic loading, and different IMCs on the stress-strain response and fatigue life of solder joints were calculated respectively. The results indicate that maximum stress-strain can be found in the second solder joint on the diagonal of IMC solder joints array, for Sn-3.9Ag-0.6Cu solder joints array the corner solder joints shows the obvious maximum stress-strain, these areas are the crack propagated locations. The stress-strain and fatigue life of solder joints is more sensitive to dwell temperature, especially to high temperature, increasing the high temperature, dwell time, or decreasing the low temperature, can reduce the stress-strain and enlarge the fatigue life of solder joints. The optimal design in the 3D IC structure has the combination of the Cu6Sn5/Cu3Sn, 373K high temperature, 233K low temperature, and 10min dwell time.