scholarly journals Scalable THz Network-On-Chip Architecture for Multichip Systems

2020 ◽  
Vol 2020 ◽  
pp. 1-15
Author(s):  
Esmaeel Tahanian ◽  
Alireza Tajary ◽  
Mohsen Rezvani ◽  
Mansoor Fateh
Keyword(s):  
Millimeter Wave ◽  
Path Loss ◽  
Network On Chip ◽  
Optimum Configuration ◽  
Novel Structure ◽  
Simulating Annealing ◽  
Parallel Plate Waveguide ◽  
High Bandwidth ◽  
Average Latency ◽  
On Chip

While THz wireless network-on-chip (WiNoC) introduces considerably high bandwidth, due to the high path loss, it cannot be used for communication between far apart nodes, especially in a multichip architecture. In this paper, we introduce a cellular and scalable architecture to reuse the frequencies of the chips. Moreover, we use a novel structure called parallel-plate waveguide (PPW) that is suitable for interchip communication. The low-loss property of this waveguide lets us increase the number of chips. Each chip has a wireless node as a gateway for communicating with other chips. To shorten the length of intra- and interchip THz links, the optimum configuration is determined by leveraging the multiobjective simulating annealing (SA) algorithm. Finally, we compare the performance of the proposed THz multichip NoC with a conventional millimeter-wave one. Our simulation results indicate that when the system scales up from four to sixteen chips, the throughput of our design is decreased about 5.8 % , while for millimeter-wave NoC, this reduction is about 21 % . Furthermore, the average latency growth of our system is only 1 % compared with about 40 % increase for the millimeter-wave NoC.

scholarly journals A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 621
Author(s):  
Wenheng Ma ◽  
Xiyao Gao ◽  
Yudi Gao ◽  
Ningmei Yu
Keyword(s):  
Great Reduction ◽  
Network On Chip ◽  
Traffic Patterns ◽  
Single Cycle ◽  
High Bandwidth ◽  
On Chip

Network-on-Chips with simple topologies are widely used due to their scalability and high bandwidth. The transmission latency increases greatly with the number of on-chip nodes. A NoC, called single-cycle multi-hop asynchronous repeated traversal (SMART), is proposed to solve the problem by bypassing intermediate routers. However, the bypass setup request of SMART requires additional pipeline stages and wires. In this paper, we present a NoC with rapid bypass channels that integrates the bypass information into each flit. In the proposed NoC, all the bypass requests are delivered along with flits at the same time reducing the transmission latency. Besides, the bypass request is unicasted in our design instead of broadcasting in SMART leading to a great reduction in wire overhead. We evaluate the NoC in four synthetic traffic patterns. The result shows that the latency of our proposed NoC is 63.54% less than the 1-cycle NoC. Compared to SMART, more than 80% wire overhead and 27% latency are reduced.

A Novel Adaptive Routing Algorithm for Network-On-Chip

2011 ◽  
Vol 474-476 ◽  
pp. 413-416
Author(s):  
Jia Jia ◽  
Duan Zhou ◽  
Jian Xian Zhang
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Experimental Results ◽  
Average Latency ◽  
On Chip

In this paper, we propose a novel adaptive routing algorithm to solve the communication congestion problem for Network-on-Chip (NoC). The strategy competing for output ports in both X and Y directions is employed to utilize the output ports of the router sufficiently, and to reduce the transmission latency and improve the throughput. Experimental results show that the proposed algorithm is very effective in relieving the communication congestion, and a reduction in average latency by 45.7% and an improvement in throughput by 44.4% are achieved compared with the deterministic XY routing algorithm and the simple XY adaptive routing algorithm.

scholarly journals Network-on-Chip Irregular Topology Optimization for Real-Time and Non-Real-Time Applications

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1196
Author(s):  
Samuel da Silva Oliveira ◽  
Bruno Motta de Carvalho ◽  
Márcio Eduardo Kreutz
Keyword(s):  
Real Time ◽  
Communication Networks ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Network On Chip ◽  
Chip Area ◽  
Average Latency ◽  
Real Time Applications ◽  
On Chip

Network-on-Chip is a good approach to working on intra-chip communication. Networks with irregular topologies may be better suited for specific applications because of their architectural nature. A good design space exploration can help the design of the network to obtain more optimized topologies. This paper proposes a way of optimizing networks with irregular topologies through the use of a genetic algorithm. The network proposed here has heterogeneous routers that aim to optimize the network and support applications with real-time tasks. The goal is to find networks that are optimized for average latency and percentage of real-time packets delivered within the deadline. The results show that we have been able to find networks that can deliver all the real-time packets, obtain acceptable latency values, and shrink the chip area.

scholarly journals Age-aware Adaptive Routing for Network-on-Chip Routing with Odd-Even Turn Model

2020 ◽  
Vol 4 (2) ◽  
Author(s):  
M. S Saliu ◽  
I. J Umoh ◽  
B.O. Sadiq ◽  
M.O Momoh
Keyword(s):  
Performance Metrics ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Point Of View ◽  
Destination Node ◽  
Traffic Patterns ◽  
Average Latency ◽  
On Chip ◽  
High Degree

This paper presents an age-aware adaptive routing for Odd-Even (OE) turn model. As packets traverse from source to destination node, their paths are defined by a given routing algorithm. For a selected routing algorithm, an efficient arbitration technique is crucial to sharing critical Network-on-Chip resources. Arbitration techniques provide high degree of local fairness from each router point of view. However, there is delay of a packet with a longer path between the source and destination nodes. In order to address this challenge an age-based arbitration technique is hereby proposed for adaptive routing with OE turn model. The age-aware adaptive routing uses an age-based arbitration technique that gives priority to oldest packet. The performance of the developed age-aware adaptive routing was evaluated using different synthetic traffic at different Packet Injection Rates (PIRs). Results were compared with the result obtained on fair arbitration technique for adaptive routing using average latency and throughput as performance metrics. The result indicated that the age-aware adaptive routing has 2.73%, 6.63 %,5.4% and 4.5 % reduction in latency under random, transpose 1 transpose 2 and bit reversal traffic patterns respectively when compared to fair arbitration adaptive routing with OE turn model. For throughput the results indicated that the age-aware adaptive routing with OE turn model has 14.22%, 13%.12% and 19% increase in throughput under random, transpose 1 transpose 2 and bit reversal traffic patterns respectively when compared to fair arbitration adaptive routing with OE turn model.

EFFICIENT SCHEME FOR CONGESTION CONTROL IN NETWORK-ON-CHIP WITH QoS CONSIDERATION

2014 ◽  
Vol 23 (09) ◽  
pp. 1450120 ◽  
Author(s):  
ADEL SOUDANI ◽  
AHMED ALDAMMAS ◽  
ABDULLAH AL-DHELAAN
Keyword(s):  
Network On Chip ◽  
Chip Multiprocessor ◽  
Multiprocessor Systems ◽  
Signaling Mechanism ◽  
Qos Management ◽  
Efficient Scheme ◽  
High Bandwidth ◽  
On Chip ◽  
Internal Architecture

Embedded distributed multimedia applications based on the use of on-chip networks for communication and messages exchange requires specific and enhanced quality of service (QoS) management. To reach the desired performances at the application level, the network-on-chip (NoC) router should implement per flit handling strategy with wide granularity. This purpose requires an enhanced internal architecture that ensures from one hand a specific management according to a service classification and from the other hand, it enhances the routing process. In this context, this paper proposes a new mechanism for QoS management in NoC. This mechanism is based on the use of central memory where flits are in-queued according to their class of service. This scheme enables an optimal flit scheduling phase and provides more capabilities to drop low important flits when the router shows congestion state symptoms. The paper presents, also, a protocol structure that fills with this architecture and introduces a signaling mechanism to make efficient the QoS management through the proposed architecture. The circuit performances and its adaptability to achieve QoS with low power processing and high bandwidth in on chip multiprocessor systems will be studied in this paper.

New design of Network on Chip Based on Virtual Routers

2016 ◽  
Vol 2 (1) ◽  
pp. 115 ◽  
Author(s):  
Mohamed Fehmi Chatmen ◽  
Adel Baganne ◽  
Rached Tourki
Keyword(s):  
Quality Of Service ◽  
Integrated Circuits ◽  
Network On Chip ◽  
Dimensional Network ◽  
3D Integrated Circuits ◽  
Average Latency ◽  
Improved Performance ◽  
Virtual Routers ◽  
On Chip

<p>Network is considered the most convenient way to communicate between different IP integrated into the same chip. Studies have been developed to propose networks with improved performance in terms of latency, power consumption, throughput and quality of service. Most of these networks have been designed based on the 2-dimensional network structure. Recently, with the introduction of the new structure of 3D integrated circuits (3D IC), new works have used this type of circuit to design 3 dimensions on-chip networks. The advantage brought by this new structure is to reduce the average number of hops crossed from the source to the destination, which improves the throughput and the average latency of the network.</p>

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