EFFICIENT SCHEME FOR CONGESTION CONTROL IN NETWORK-ON-CHIP WITH QoS CONSIDERATION

2014 ◽  
Vol 23 (09) ◽  
pp. 1450120 ◽  
Author(s):  
ADEL SOUDANI ◽  
AHMED ALDAMMAS ◽  
ABDULLAH AL-DHELAAN
Keyword(s):  
Network On Chip ◽  
Chip Multiprocessor ◽  
Multiprocessor Systems ◽  
Signaling Mechanism ◽  
Qos Management ◽  
Efficient Scheme ◽  
High Bandwidth ◽  
On Chip ◽  
Internal Architecture

Embedded distributed multimedia applications based on the use of on-chip networks for communication and messages exchange requires specific and enhanced quality of service (QoS) management. To reach the desired performances at the application level, the network-on-chip (NoC) router should implement per flit handling strategy with wide granularity. This purpose requires an enhanced internal architecture that ensures from one hand a specific management according to a service classification and from the other hand, it enhances the routing process. In this context, this paper proposes a new mechanism for QoS management in NoC. This mechanism is based on the use of central memory where flits are in-queued according to their class of service. This scheme enables an optimal flit scheduling phase and provides more capabilities to drop low important flits when the router shows congestion state symptoms. The paper presents, also, a protocol structure that fills with this architecture and introduces a signaling mechanism to make efficient the QoS management through the proposed architecture. The circuit performances and its adaptability to achieve QoS with low power processing and high bandwidth in on chip multiprocessor systems will be studied in this paper.

Network-on-Chip virtualization in Chip-Multiprocessor Systems

2012 ◽  
Vol 58 (3-4) ◽  
pp. 126-139 ◽  
Author(s):  
Francisco Triviño ◽  
José L. Sánchez ◽  
Francisco J. Alfaro ◽  
José Flich
Keyword(s):  
Network On Chip ◽  
Chip Multiprocessor ◽  
Multiprocessor Systems ◽  
On Chip

scholarly journals A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 621
Author(s):  
Wenheng Ma ◽  
Xiyao Gao ◽  
Yudi Gao ◽  
Ningmei Yu
Keyword(s):  
Great Reduction ◽  
Network On Chip ◽  
Traffic Patterns ◽  
Single Cycle ◽  
High Bandwidth ◽  
On Chip

Network-on-Chips with simple topologies are widely used due to their scalability and high bandwidth. The transmission latency increases greatly with the number of on-chip nodes. A NoC, called single-cycle multi-hop asynchronous repeated traversal (SMART), is proposed to solve the problem by bypassing intermediate routers. However, the bypass setup request of SMART requires additional pipeline stages and wires. In this paper, we present a NoC with rapid bypass channels that integrates the bypass information into each flit. In the proposed NoC, all the bypass requests are delivered along with flits at the same time reducing the transmission latency. Besides, the bypass request is unicasted in our design instead of broadcasting in SMART leading to a great reduction in wire overhead. We evaluate the NoC in four synthetic traffic patterns. The result shows that the latency of our proposed NoC is 63.54% less than the 1-cycle NoC. Compared to SMART, more than 80% wire overhead and 27% latency are reduced.

Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

2010 ◽  
pp. 28-66 ◽  
Author(s):  
Mário P. Véstias ◽  
Horácio C. Neto
Keyword(s):  
Quality Of Service ◽  
Power Consumption ◽  
First Generation ◽  
Networks On Chip ◽  
Dynamically Reconfigurable ◽  
Systems On Chip ◽  
High Bandwidth ◽  
Area Occupation ◽  
On Chip

The recent advances in IC technology have made it possible to implement systems with dozens or even hundreds of cores in a single chip. With such a large number of cores communicating with each other there is a strong pressure over the communication infrastructure to deliver high bandwidth, low latency, low power consumption and quality of service to guarantee real-time functionality. Networks-on-Chip are definitely becoming the only acceptable interconnection structure for today’s multiprocessor systems-on-chip (MPSoC). The first generation of NoC solutions considers a regular topology, typically a 2D mesh. Routers and network interfaces are mainly homogeneous so that they can be easily scaled up and modular design is facilitated. All advantages of a NoC infrastructure were proved with this first generation of NoC solutions. However, NoCs have a relative area and speed overhead. Application specific systems can benefit from heterogeneous communication infrastructures providing high bandwidth in a localized fashion where it is needed with improved area. The efficiency of both homogeneous and heterogeneous solutions can be improved if runtime changes are considered. Dynamically or runtime reconfigurable NoCs are the second generation of NoCs since they represent a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance and quality of service compared to the previous generation where the architecture is decided at design time. This chapter discusses the static and runtime customization of routers and presents results with networks-on-chip with static and adaptive routers. Runtime adaptive techniques are analyzed and compared to each other in terms of area occupation and performance. The results and the discussion presented in this chapter show that dynamically adaptive routers are fundamental in the design of NoCs to satisfy the requirements of today’s systems-on-chip.

Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms

2014 ◽  
Vol 29 (1) ◽  
pp. 21-37 ◽  
Author(s):  
Fang Lv ◽  
Hui-Min Cui ◽  
Lei Wang ◽  
Lei Liu ◽  
Cheng-Gang Wu ◽  
...  
Keyword(s):  
Chip Multiprocessor ◽  
Multiprocessor Systems ◽  
Batch Mode ◽  
On Chip

scholarly journals Energy characteristic of a processor allocator and a network-on-chip

2011 ◽  
Vol 21 (2) ◽  
pp. 385-399 ◽  
Author(s):  
Dawid Zydek ◽  
Henry Selvaraj ◽  
Grzegorz Borowik ◽  
Tadeusz Łuba
Keyword(s):  
Energy Characteristic ◽  
Network On Chip ◽  
Energy Model ◽  
Chip Multiprocessor ◽  
Energy Estimation ◽  
Processing Elements ◽  
Chip Processing ◽  
On Chip ◽  
Allocation Algorithms ◽  
2D Torus

Energy characteristic of a processor allocator and a network-on-chip Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.

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