FPGA Implementation of A∗ Algorithm for Real-Time Path Planning

The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator’s architecture called A∗ accelerator has been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A∗ accelerator. Experiments show that the hardware accelerator achieves 37–75 times performance enhancement relative to software implementation. It is suitable for real-time path-planning applications.

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A Hardware Accelerator for the Inference of a Convolutional Neural network

Ciencia e Ingeniería Neogranadina ◽

10.18359/rcin.4194 ◽

2019 ◽

Vol 30 (1) ◽

pp. 107-116 ◽

Cited By ~ 1

Author(s):

Edwin González ◽

Walter D. Villamizar Luna ◽

Carlos Augusto Fajardo Ariza

Keyword(s):

Field Programmable Gate Array ◽

System On Chip ◽

Software Implementation ◽

Hardware Accelerator ◽

Processing Scheme ◽

Field Programmable ◽

Computationally Intensive ◽

On Chip ◽

Memory Resources ◽

Better Than

Convolutional Neural Networks (CNNs) are becoming increasingly popular in deep learning applications, e.g. image classification, speech recognition, medicine, to name a few. However, the CNN inference is computationally intensive and demanding a large among of memory resources. In this work is proposed a CNN inference hardware accelerator, which was implemented in a co-processing scheme. The aim is to reduce the hardware resources and achieve the better possible throughput. The design was implemented in the Digilent Arty Z7-20 development board, which is based on System on Chip (SoC) Zynq-7000 of Xilinx. Our implementation achieved a of accuracy for the MNIST database using only 12-bits fixed-point format. The results show that the co-processing scheme operating at a conservative speed of 100 MHz can identify around 441 images per second, which is about 17% times faster than a 650 MHz - software implementation. It is difficult to compare our results against other implementations based on Field-Programmable Gate Array (FPGA), because the others implementations are not exactly like ours. However, some comparisons, regarding the logical resources used and accuracy, suggest that our work could be better than previous works.

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Real-time path planning for low altitude flight based on A* algorithm and TF/TA algorithm

2012 IEEE International Conference on Automation Science and Engineering (CASE) ◽

10.1109/coase.2012.6386506 ◽

2012 ◽

Cited By ~ 2

Author(s):

He Wang ◽

Qing Li ◽

Nong Cheng

Keyword(s):

Path Planning ◽

Real Time ◽

A Algorithm ◽

Time Path ◽

Low Altitude

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Feature Extraction Acceleration to Stabilize Execution Time for Real-Time Applications in Low-Cost Embedded Systems

Journal of Circuits System and Computers ◽

10.1142/s0218126620200030 ◽

2019 ◽

Vol 29 (06) ◽

pp. 2020003

Author(s):

Taek Kyu Kim

Keyword(s):

Feature Extraction ◽

Embedded Systems ◽

Real Time ◽

Execution Time ◽

Field Programmable Gate Array ◽

Low Cost ◽

Hardware Accelerator ◽

Simple Arithmetic ◽

Field Programmable ◽

Gate Array

Extracted features are widely used for image processing. Many research endeavors have been undertaken to extract significant features of fast moving images. Appropriate algorithm processing is necessary to extract features and provide features to the other modules in real time with low-cost embedded systems. The features from accelerated segment test (FAST) algorithm is renowned for feature extraction. FAST is composed of simple arithmetic operators. In this study, FAST is employed to implement the hardware accelerator in a field-programmable gate array for small embedded systems. Meanwhile, the threshold value in FAST affects the number of extracted features and the execution time. The precarious execution time makes it difficult for the system to schedule the timing of system functions and thus degrades the performance. An appropriate method is necessary to stabilize the execution time. A dynamic threshold controller in a FAST hardware accelerator is thus proposed to enable a stable execution time. A proportional integral controller composed of an adder, subtractor, and shifter is applied for low design implementation costs. The proposed approach occupies 2,263 slice flip-flops, 3,498 look-up tables, and 17 block RAMs in a Xilinx Virtex 5 FX field-programmable gate array. It requires 3.87[Formula: see text]ms for continuous 800×480 images from the KITTI benchmark.

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Path Planning for Batch Picking of Warehousing and Logistics Robots Based on Modified A* Algorithm

International Journal of Online Engineering (iJOE) ◽

10.3991/ijoe.v14i11.9527 ◽

2018 ◽

Vol 14 (11) ◽

pp. 176 ◽

Cited By ~ 1

Author(s):

Li-Mei Duan

Keyword(s):

Path Planning ◽

Real Time ◽

Visual Programming ◽

Simulation System ◽

Time Cost ◽

Warehouse Management ◽

A Algorithm ◽

Research Results ◽

Time Path ◽

Solid Foundation

<p class="0abstract"><span lang="EN-US">To make the picking path planning of warehousing and logistics robot in warehouse more efficient and real-time, a path planning for batch picking of warehousing and logistics robots based on the modified A* algorithm was put forward. First of all, the path planning of the single robot batch picking was realized. Then, the time cost was introduced to further improve the A* algorithm to realize the batch picking path planning of the multi-warehouse logistics robots. Finally, according to the algorithm proposed, .Net visual programming technology was applied to build a complete warehouse logistics robot picking path planning simulation system to verify the effectiveness of the algorithm proposed. The research results showed that the algorithm proposed could meet the needs of efficient and real-time path planning in the process of completing batch picking tasks. To sum up, it lays a solid foundation for the realization of intelligent and fully automated warehouse management.</span></p>

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