scholarly journals A Modified Diagonal Mesh Shuffle Exchange Interconnection Network

2017 ◽  
Vol 7 (2) ◽  
pp. 1042
Author(s):  
Akash Punhani ◽  
Pardeep Kumar ◽  
Nitin Nitin
Keyword(s):  
Interconnection Network ◽  
Average Distance ◽  
Routing Algorithm ◽  
The Other ◽  
Mesh Network ◽  
Traffic Patterns ◽  
Boundary Node ◽  
Exchange Network ◽  
Shuffle Exchange Network ◽  
2D Torus

Interconnection network is an important part of the digital system. The interconnection mainly describes the topology of the network along with the routing algorithm and flow control mechanism. The topology of the network plays an important role on the performance of the system. Mesh interconnection network was the simplest topology, but has the limited bisection bandwidth on the other hand torus and diagonal mesh was having long links. The Modified diagonal mesh network tried to replace the torodial links but was having more average path length so in proposed topology we have tried to improve the average distance using shuffle exchange network over the boundary node. In this paper, we propose the architecture of Modified Diagonal Mesh Shuffle Exchange Interconnection Network. This Modified Diagonal Mesh Shuffle Exchange Interconnection network have been compared with four popular topologies that are simple 2D Mesh, 2D Torus, Diagonal Mesh and Modified Diagonal Mesh Interconnection Network on the four traffic patterns such as Bit Complement traffic, Neighbor traffic, Tornado traffic and Uniform traffic are used for comparisonand performance analysis. We have performed the analysis with a 5% and 10% of hotspot on the Uniform Traffic. The simulation results shows that the proposed topology is performed better on bit complement traffic and can also handle the other traffic up to certain level.

scholarly journals 3D NoC Network using Adaptive Algorithm for 8x8x4 Mesh

2019 ◽  
Vol 8 (9S) ◽  
pp. 893-899
Keyword(s):  
Adaptive Algorithm ◽  
Routing Algorithm ◽  
Mesh Network ◽  
Traffic Patterns ◽  
3D Mesh ◽  
Limited Bandwidth ◽  
Traffic Pattern ◽  
Traffic Distribution ◽  
Maximum Delay ◽  
Injection Ratio

This paper presents a qualitative analysis of 3D routing algorithm in 8x8x4 mesh network topology. The traffic distribution in 3D routing algorithm has limited bandwidth along vertical links. Different traffic patterns were used during simulation. The simulation is performed on different traffic pattern. The proposed 3D algorithm has been used to perform better in terms of latency and throughput in comparison with existing routing algorithm. The simulation is done with synthetic traffic pattern in a 8×8×4 3D mesh system design which shows that with existing routing algorithm the network is powerful and steady under various traffic patterns, A weighted adaptive routing algorithm for 8×8×4 3D mesh NoC frameworks with arbitrary traffic pattern reveals to accomplish critical execution improvement in terms of Maximum delay and throughput with existing XYZ routing algorithm. Throughput for WARA at packet injection ratio 0.26 is 0.0009893 and maximum delay at packet injection ratio 0.26 is 976.

scholarly journals Low latency Path Aware XY-X Routing Algorithm for NoC Architectures

2018 ◽  
Vol 7 (2.7) ◽  
pp. 763
Author(s):  
Venkateswara Rao Musala ◽  
T V Rama Krishna
Keyword(s):  
High Performance ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Destination Node ◽  
Specific Information ◽  
Traffic Patterns ◽  
Traffic Conditions ◽  
Trade Offs ◽  
On Chip

Route specific information with the SoC needs a great deal of wiring, which increases the Resistance & Capacitance (RC) component of the system. Network on Chip (NoC) is utilized as the interface to address the problems in SoC, On-chip interconnection network in NoC has gained more consideration over steadfast wiring and buses, like lower latency, scalability and high performance. Present routing algorithms in NoC is suffered from load balancing at incarnation networks under non-uniform traffic conditions, causes increase the NoC trade-offs (latency and throughput). Adaptive routing is a technique to progress the load balance, but previous adaptive routing techniques used uniform traffic patterns to form the routing decisions. This paper proposes a new approach at non- uniform traffic patterns in channel state and path specific, Path Aware Routing (PAR XY-X) uses a timeout piggybacking for acknowledgement and load shedding to avoid congestion which choose optimistic path calculation unit to connect the destination node without glue logic decisions in routing. PAR XY-X outperforms the Normal XY routing by 20% and 33% with respect to Avg.latency and throughput.

Design of Fault Tolerant Shuffle Exchange Gamma Interconnection Network Layouts

2017 ◽  
Vol 17 (02) ◽  
pp. 1750005 ◽  
Author(s):  
GAURAV KHANNA ◽  
RAJESH MISHRA ◽  
S. K. CHATURVEDI
Keyword(s):  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Cost Effective ◽  
Disjoint Paths ◽  
Multiple Processors ◽  
Memory Modules ◽  
Telephone Industry ◽  
Exchange Network ◽  
Shuffle Exchange Network

Advancement in technology has resulted in increased computing power with the use of multiple processors within a system. These multiple processors need to communicate with each other and with memory modules. Multistage Interconnection Networks (MINs) provide a communication medium in such multi-processor systems by interconnecting a number of processors and memory modules. Besides, MINs also provide a cost effective substitute to costly crossbars in parallel computers and switching systems in telephone industry. This paper introduces two new fault-tolerant MINs named as Shuffle Exchange Gamma Interconnection Networks (SEGIN-1 and SEGIN-2). SEGIN-1 and SEGIN-2 can be obtained by altering Shuffle Exchange Network with one extra stage (SEN+) and provide two disjoint paths similar to it. Performance of SEGIN-1 and SEGIN-2 has been evaluated in terms of alternative paths, disjoint paths, reliability and hardware cost, and is compared with some very famous MINs like Shuffle Exchange Network (SEN), Shuffle Exchange Network with one extra stage (SEN+), Shuffle Exchange Network with two extra stage (SEN+2), Extra Stage Cube (ESC) and Gamma Interconnection Network (GIN). Results suggest that SEGINs surpass all the compared networks; hence, the proposed designs seem to be suitable for implementing practical interconnection networks.

Architecture and Network-on-Chip Implementation of a New Hierarchical Interconnection Network

2014 ◽  
Vol 24 (02) ◽  
pp. 1540006 ◽  
Author(s):  
M. M. Hafizur Rahman ◽  
Rizal Mohd Nor ◽  
Tengku Mohd Bin Tengku Sembok ◽  
M. A. H. Akhand
Keyword(s):  
Mesh Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Average Distance ◽  
Small Diameter ◽  
Network On Chip ◽  
Mesh Network ◽  
Minimal Distance ◽  
Bisection Width ◽  
On Chip

A Midimew-connected Mesh Network (MMN) is a minimal distance mesh with wrap-around links network of multiple basic modules (BMs), in which the BMs are 2D-mesh networks that are hierarchically interconnected for higher-level networks. In this paper, we present the architecture of the MMN, addressing of node, routing of message, and evaluate the static network performance of MMN, TESH, mesh and torus networks. In addition, we propose the network-on-chip (NoC) implementation of MMN. With innovative combination of diagonal and hierarchical structure, the MMN possesses several attractive features, including constant degree, small diameter, low cost, small average distance, moderate bisection width and high fault tolerant performance than that of other conventional and hierarchical interconnection networks. The simple architecture of MMN is also highly suitable for NoC implementation. To implement all the links of level-3 MMN, only four layers are needed which is feasible with current and future VLSI technologies.

scholarly journals Mean Time to Failure Analysis in Shuffle Exchange Systems

2019 ◽  
Vol 9 (1) ◽  
pp. 3419-3422
Keyword(s):  
Network Performance ◽  
Interconnection Network ◽  
Time To Failure ◽  
Switching Element ◽  
Mean Time To Failure ◽  
The Mean ◽  
Basic Network ◽  
Exchange Network ◽  
Shuffle Exchange Network ◽  
Mean Time

Multistage Interconnection Network (MIN) has been researched for the interconnection implementation of switches and multiprocessors. The topology of the interconnection, the number of stage and the switching element used in the network distinguish between each MIN's tolerance of failure.This paper introduces a topology called Replicated Shuffle Exchange Network and Replicated Augmented Shuffle Exchange Network. A replicated technique is described for making the network more reliable. The replicated technique results in reduced the Mean Time to Failure in the network. Performance measurement shows that replicated network achieve a significant improvement over a basic network have been measured.

EFFICIENT ROUTING ALGORITHMS FOR GENERALIZED SHUFFLE-EXCHANGE NETWORKS

2009 ◽  
Vol 01 (02) ◽  
pp. 267-281 ◽  
Author(s):  
JAMES K. LAN ◽  
WELL Y. CHOU ◽  
CHIUYUAN CHEN
Keyword(s):  
Explicit Formula ◽  
Interconnection Networks ◽  
Routing Algorithm ◽  
Routing Algorithms ◽  
Multistage Interconnection Networks ◽  
Exchange Networks ◽  
Routing Table ◽  
Computation Process ◽  
Exchange Network ◽  
Shuffle Exchange Network

The shuffle-exchange network has been proposed as a popular architecture for multistage interconnection networks. In 1991, Padmanabhan introduced the generalized shuffle-exchange network (GSEN) and proposed an efficient routing algorithm. Later, Chen et al. further enhanced the GSEN with bidirectional links and proposed the bidirectional GSEN (BGSEN). A BGSEN consists of the forward and the backward network. Based on the idea of inversely using the control tag generated by Padmanabhan's algorithm, Chen et al. proposed a routing algorithm for the backward network. Recently, Chen and Lou also proposed a routing algorithm for the backward network. It should be noted, however, that Padmanabhan's algorithm is actually an explicit formula for computing the control tag for routing and takes only O(1) time. Neither the algorithm of Chen et al. nor the algorithm of Chen and Lou provides an explicit formula for computing the control tag for routing and both algorithms take at least Ω(n) time, where n + 1 is the number of stages in the BGSEN. This paper attempts to propose an explicit formula for computing the control tag for routing in the backward network. We will demonstrate how this formula greatly simplifies the computation process and how it leads to efficient routing algorithms. In particular, an O(1)-time one-to-one routing algorithm and an efficient routing-table construction algorithm have been proposed.

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