An Analog Memory Circuit for Spiking Silicon Neurons

1997 ◽  
Vol 9 (2) ◽  
pp. 419-440 ◽  
Author(s):  
John G. Elias ◽  
David P. M. Northmore ◽  
Wayne Westerman
Keyword(s):  
Dendritic Tree ◽  
Simple Circuit ◽  
Bistable Behavior ◽  
Silicon Neuron ◽  
Integrate And Fire ◽  
Memory Circuit ◽  
Analog Memory ◽  
Silicon Neurons ◽  
Time Periods ◽  
Spike Firing

A simple circuit is described that functions as an analog memory whose state and dynamics are directly controlled by pulsatile inputs. The circuit has been incorporated into a silicon neuron with a spatially extensive dendritic tree as a means of controlling the spike firing threshold of an integrate-and-fire soma. Spiking activity generated by the neuron itself and by other units in a network can thereby regulate the neuron's excitability over time periods ranging from milliseconds to many minutes. Experimental results are presented showing applications to temporal edge sharpening, bistable behavior, and a network that learns in the manner of classical conditioning.

Spike Train Processing by a Silicon Neuromorph: The Role of Sublinear Summation in Dendrites

1996 ◽  
Vol 8 (6) ◽  
pp. 1245-1265 ◽  
Author(s):  
David P. M. Northmore ◽  
John G. Elias
Keyword(s):  
Spike Train ◽  
Input Pulse ◽  
Dendritic Tree ◽  
Spike Generation ◽  
Linear Summation ◽  
Cable Structure ◽  
Integrate And Fire ◽  
Local Saturation ◽  
Theoretical Analyses

A dendritic tree, as part of a silicon neuromorph, was modeled in VLSI as a multibranched, passive cable structure with multiple synaptic sites that either depolarize or hyperpolarize local “membrane patches,” thereby raising or lowering the probability of spike generation of an integrate-and-fire “soma.” As expected from previous theoretical analyses, contemporaneous synaptic activation at widely separated sites on the artificial tree resulted in near-linear summation, as did neighboring excitatory and inhibitory activations. Activation of synapses of the same type close in time and space produced local saturation of potential, resulting in spike train processing capabilities not possible with linear summation alone. The resulting sublinear synaptic summation, as well as being physiologically plausible, is sufficient for a variety of spike train processing functions. With the appropriate arrangement of synaptic inputs on its dendritic tree, a neuromorph was shown to discriminate input pulse intervals and patterns, pulse train frequencies, and detect correlation between input trains.

scholarly journals Reliability-Aware Design of Spike-Event Neuromorphic Circuits

2021 ◽  
Author(s):  
Jani Babu Shaik ◽  
Siona Menezes Picardo ◽  
Sonal Singhal ◽  
Nilesh Goel
Keyword(s):  
Large Scale ◽  
Vlsi Circuits ◽  
Performance Parameters ◽  
Carrier Injection ◽  
Neuromorphic Circuits ◽  
Integrate And Fire ◽  
Bias Temperature Instability ◽  
Large Scale Integration ◽  
Silicon Neurons ◽  
Scale Integration

Very Large Scale Integration (VLSI) based neuromorphic circuits also known as Silicon Neurons (SiNs) emulate the electrophysiological behavior of biological neurons. With the advancement in technology, neuromorphic systems also lead to various reliability issues and hence making their study important. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are the two major reliability issues present in VLSI circuits. In this work, we have investigated the combined effect of BTI and HCI on the two types of integrate-and-fire based SiNs namely (a) Axon-Hillock and (b) Simplified Leaky integrate-and-fire circuits using their key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. Proposed reliability-aware designs show negligible deviation in performance parameters after aging. The time-zero process variability analysis is also carried out for proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.<br>

scholarly journals An experimental prediction: granule cells can perform linearly non-separable computations

2021 ◽  
Author(s):  
Romain Daniel Caze
Keyword(s):  
Nervous System ◽  
Neuron Model ◽  
Granule Cells ◽  
Cerebellar Granule Cells ◽  
Large Fraction ◽  
Dendritic Tree ◽  
Cerebellar Granule ◽  
Integrate And Fire ◽  
Experimental Prediction ◽  
Artificial Network

Multiple studies show how dendrites might extend some neurons' computational capacity. These studies leave a large fraction of the nervous system unexplored. Here we demonstrate how a modest dendritic tree can allow cerebellar granule cells to implement linearly non-separable computations. Granule cells' dendrites do not spike and these cells' membrane voltage is isopotential. Conjunction of Boolean algebra and biophysical modelling enable us to make an experimental prediction. Granule cells can perform linearly non-separable computations. The standard neuron model used in the artificial network, aka the integrate and fire, cannot perform such type of computations. Confirming the prediction we provide in the present work would change how we understand the nervous system.

A Low-Power, Digitally-Controlled, Multi-Stable, CMOS Analog Memory Circuit

2020 ◽  
Author(s):  
Melvin D. Edwards ◽  
Hamza Al Maharmeh ◽  
Nabil J. Sarhan ◽  
Mohammed Ismail ◽  
Mohammad Alhawari
Keyword(s):  
Low Power ◽  
Memory Circuit ◽  
Analog Memory ◽  
Digitally Controlled

scholarly journals Reliability-Aware Design of Spike-Event Neuromorphic Circuits

2021 ◽  
Author(s):  
Jani Babu Shaik ◽  
Siona Menezes Picardo ◽  
Sonal Singhal ◽  
Nilesh Goel
Keyword(s):  
Large Scale ◽  
Vlsi Circuits ◽  
Performance Parameters ◽  
Carrier Injection ◽  
Neuromorphic Circuits ◽  
Integrate And Fire ◽  
Bias Temperature Instability ◽  
Large Scale Integration ◽  
Silicon Neurons ◽  
Scale Integration

Very Large Scale Integration (VLSI) based neuromorphic circuits also known as Silicon Neurons (SiNs) emulate the electrophysiological behavior of biological neurons. With the advancement in technology, neuromorphic systems also lead to various reliability issues and hence making their study important. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are the two major reliability issues present in VLSI circuits. In this work, we have investigated the combined effect of BTI and HCI on the two types of integrate-and-fire based SiNs namely (a) Axon-Hillock and (b) Simplified Leaky integrate-and-fire circuits using their key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. Proposed reliability-aware designs show negligible deviation in performance parameters after aging. The time-zero process variability analysis is also carried out for proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.<br>

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