Design and Implementation of NAND Simulator for Bit Error Rate Model

2017 ◽  
Vol 23 (12) ◽  
pp. 12780-12784
Author(s):  
Kijin Kim ◽  
Seung-Ho Lim
2013 ◽  
Vol 380-384 ◽  
pp. 757-760
Author(s):  
Luo Jun ◽  
Lu Wen Jun ◽  
Ye Fei ◽  
Sun Shuang Xi ◽  
Pe Dong Hui

UAV wireless channel is the core of their communications systems, this paper designed a stepper adjustable independently programmable power attenuation device and contains three functional subsystems to achieve a radio channel test equipment for testing wireless channel launch power attenuation, receiver sensitivity and receiver bit error rate and other key technical indicators.


2014 ◽  
Vol 672-674 ◽  
pp. 883-887
Author(s):  
Li Min Chang ◽  
Qing Wei Dong ◽  
Ye Zhan

The paper briefly introduces the structure principle and excellent characteristics of protograph LDPC codes and designs the serial encoding circuit based on FPGA. On the basis of the further study of Belief Propagation (BP) algorithm, λ-min algorithm and A - min algorithm, decoder is designed adopting the complexity and performance eclectic mixed decoding algorithm. Meanwhile, it is verified by the simulation. The result shows that coding gain can be up to about 6 to 8 db, if it meets the requirements of 10-5bit error rate.


2019 ◽  
Vol E102.B (5) ◽  
pp. 1000-1004
Author(s):  
Naruki SHINOHARA ◽  
Koji IGARASHI ◽  
Kyo INOUE
Keyword(s):  

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