TAP (Time, Area, and Power) trade off at lower geometries in data center ASIC: A deep dive into executional view and results

Author(s):  
Ruchita Shah* ◽  
Nilesh Ranpura* ◽  
Bhavesh Soni*
Keyword(s):  
Author(s):  
Sambhu Nath Pradhan ◽  
Santanu Chattopadhyay

2011 ◽  
Vol 20 (06) ◽  
pp. 1019-1035 ◽  
Author(s):  
SAMBHU NATH PRADHAN ◽  
M. TILAK KUMAR ◽  
SANTANU CHATTOPDHYAY

In this paper, a heuristic based on genetic algorithm to realize multi-output Boolean function as three-level AND-OR-XOR network performing area power trade-off is presented. All the previous works dealt with the minimization of number of product terms only in the two sum-of-product-expressions representing a Boolean function during AND-OR-XOR network synthesis. To the best of knowledge this is the first ever effort to incorporate total power, that is, dynamic and leakage power along with the area (in terms of number of product terms) during three-level AND-OR-XOR networks synthesis. The synthesis process, without changing the delay performance results in lesser number of product terms compared to those reported in the literature. It also enumerates the trade-offs present in the solution space for different weights associated with area, dynamic power, and leakage power of the resulting circuit.


Author(s):  
Piero Zappi ◽  
Clemens Lombriser ◽  
Thomas Stiefmeier ◽  
Elisabetta Farella ◽  
Daniel Roggen ◽  
...  

2019 ◽  
Vol 37 (3) ◽  
pp. 296-310 ◽  
Author(s):  
Ákos Ladányi ◽  
Tibor Cinkler

2014 ◽  
Vol 436 ◽  
pp. 18-19
Author(s):  
Kenneth Goossens ◽  
Linde A.C. De Grande ◽  
Thomas Keller ◽  
Stefan Weber ◽  
Linda M. Thienpont

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