2013 ◽  
Vol 42 (2) ◽  
pp. 132-134
Author(s):  
徐光辉 XU Guang-hui ◽  
柴广跃 CHAI Guang-yue ◽  
黄长统 HUANG Chang-tong ◽  
何黎明 HE Li-ming ◽  
徐健 XU Jian ◽  
...  

2016 ◽  
Vol 16 (10) ◽  
pp. 3620-3626 ◽  
Author(s):  
Davide Marano ◽  
Giovanni Bonanno ◽  
Salvatore Garozzo ◽  
Alessandro Grillo ◽  
Giuseppe Romeo

2013 ◽  
Vol 2013 (1) ◽  
pp. 000233-000233
Author(s):  
Niranjan Kumar

TSVs are used to carry power/ground and signals straight to the heart of the logic/memory devices where all the intricate and busy architectures lie. I consider it like the downtown area inside a city where the real estate is more expensive and requires intricate design and execution. As a result in case of the TSVs, there is no room for electrical degradation and stress interaction with transistor devices (keep out zone). The Cu protrusion, it's interaction with the intricate local interconnects (M1 and below structures), the current leakage, capacitance, reliability, become highly critical to fully achieve the power per watt advantage of the TSVs. As a result, a thorough electrical characterization of TSVs with varying film properties and the process window becomes very critical for integration with the 20nm node (and below) devices. In this paper we will discuss implementation of modified oxide liner, barrier/seed, ECD fill and CMP of films to achieve robust TSVs for electrical parameter extraction. We will closely examine the impact of these film properties on the electrical performance and its repeatability to achieve wide process windows. Such studies are expected to improve manufacturing yields of TSV product wafers at fabs/foundries. Alternately, we will present detailed metrology studies of two temporary bond method/adhesive systems as it progresses through the thin wafer downstream processes (via-reveal processes). This exercise is targeted to address productivity and yield challenges with thin wafer processing (backside via-reveal process). We will attempt to demonstrate a robust temporary bond/adhesive system that exhibits no thin wafer damage/wrinkling and no edge profile degradation issues over repeated runs (production like). This study will help to characterize the adhesive and low temperature passivation film interfaces in details to support the thin wafer processing robustness for TSV manufacturing.


2020 ◽  
Vol 29 (13) ◽  
pp. 2050215
Author(s):  
A. Akkaya ◽  
E. Ayyıldız

We prepared a simple program for basic electrical measurements and parameter extraction from these measurements of metal–semiconductor (MS) contacts. In this paper, we introduce a basic electrical parameter calculation software (SeCLaS-PC) for semiconductor laboratories from the temperature-dependent/independent current–voltage ([Formula: see text]–[Formula: see text]), capacitance– voltage ([Formula: see text]–[Formula: see text]) and capacitance–frequency ([Formula: see text]–[Formula: see text]) measurement results. SeCLaS-PC program was developed using Keysight VEE Pro (Visual Engineering Environment) software and the program has a user-friendly graphical interface. More than 50 device parameters can be easily obtained, using different methods, from the [Formula: see text]–[Formula: see text], temperature-dependent [Formula: see text]–[Formula: see text] and temperature-dependent [Formula: see text]–[Formula: see text] measurement results for one device, with our SeCLaS-PC program.


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