On Chip Interconnects for Multicore Architectures

2013 ◽  
pp. 285-298
Author(s):  
Prasun Ghosal ◽  
Soumyajit Poddar
Keyword(s):  
Multicore Architectures ◽  
On Chip

Performance of Gaussian and Non-Gaussian Synthetic Traffic on Networks-on-Chip

2017 ◽  
Vol 8 (2) ◽  
pp. 33-42 ◽  
Author(s):  
Amit Chaurasia ◽  
Vivek Kumar Sehgal
Keyword(s):  
Packet Loss ◽  
Marginal Distribution ◽  
Loss Probability ◽  
Multicore Architectures ◽  
Traffic Patterns ◽  
Networks On Chip ◽  
Real Time Traffic ◽  
Link Utilization ◽  
On Chip ◽  
Non Gaussian

In this paper, we have worked on the bursty synthetic traffic for Gaussian and Non-Gaussian traffic traces on the NoC architecture. This is the first study on the performance of Gaussian and Non-Gaussian application traffic on the multicore architectures. The real-time traffic having the marginal distribution are Non-Gaussian in nature, so any analytical studies or simulations will not be accurate, and does not capture the true characteristics of application traffic. Simulation is performed on synthetic generated traces for Gaussian and Non-Gaussian traffic for different traffic patterns. The performance of the two traffics is validated by simulating the parameters of packet loss-probability, average link-utilization & average end-to-end latency shows that the Non-Gaussian traffic captures the burstiness more effectively as compared to the Gaussian traffic for the desired application.

PARALLEL GAUSS-SEIDEL ON A TORUS NETWORK-ON-CHIP ARCHITECTURE

2012 ◽  
Vol 13 (01n02) ◽  
pp. 1250001 ◽  
Author(s):  
MOHAMMAD H. AL-TOWAIQ ◽  
KHALED DAY
Keyword(s):  
Linear Equations ◽  
Network On Chip ◽  
Multicore Architectures ◽  
Processing Elements ◽  
Recent Developments ◽  
Systems Of Linear Equations ◽  
Large Systems ◽  
On Chip ◽  
Large Linear Systems ◽  
Torus Network

Network-on-chip multicore architectures with a large number of processing elements are becoming a reality with the recent developments in technology. In these modern systems the processing elements are interconnected with regular network-on-chip (NoC) topologies such as meshes and trees. In this paper we propose a parallel Gauss-Seidel (GS) iterative algorithm for solving large systems of linear equations on a torus NoC architecture. The proposed parallel algorithm is O (Nn2/k2) time complexity for solving a system with matrix of order n on a k × k torus NoC architecture with N iterations assuming n and N are large compared to k (i.e. for large linear systems that require a large number of iterations). We show that under these conditions the proposed parallel GS algorithm has near optimal speedup.

scholarly journals Effective On-Chip Communication for Message Passing Programs on Multi-Core Processors

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2681
Author(s):  
Joonmoo Huh ◽  
Deokwoo Lee
Keyword(s):  
Parallel Programming ◽  
Shared Memory ◽  
Message Passing ◽  
Programming Model ◽  
Multicore Architectures ◽  
Worst Case ◽  
High Performing ◽  
Parallel Programming Model ◽  
On Chip ◽  
Sharing Patterns

Shared memory is the most popular parallel programming model for multi-core processors, while message passing is generally used for large distributed machines. However, as the number of cores on a chip increases, the relative merits of shared memory versus message passing change, and we argue that message passing becomes a viable, high performing, and parallel programming model. To demonstrate this hypothesis, we compare a shared memory architecture with a new message passing architecture on a suite of applications tuned for each system independently. Perhaps surprisingly, the fundamental behaviors of the applications studied in this work, when optimized for both models, are very similar to each other, and both could execute efficiently on multicore architectures despite many implementations being different from each other. Furthermore, if hardware is tuned to support message passing by supporting bulk message transfer and the elimination of unnecessary coherence overheads, and if effective support is available for global operations, then some applications would perform much better on a message passing architecture. Leveraging our insights, we design a message passing architecture that supports both memory-to-memory and cache-to-cache messaging in hardware. With the new architecture, message passing is able to outperform its shared memory counterparts on many of the applications due to the unique advantages of the message passing hardware as compared to cache coherence. In the best case, message passing achieves up to a 34% increase in speed over its shared memory counterpart, and it achieves an average 10% increase in speed. In the worst case, message passing is slowed down in two applications—CG (conjugate gradient) and FT (Fourier transform)—because it could not perform well on the unique data sharing patterns as its counterpart of shared memory. Overall, our analysis demonstrates the importance of considering message passing as a high performing and hardware-supported programming model on future multicore architectures.

Fuzzy Logic-Based DSE Engine: Reconfiguration for Optimization of Multicore Architectures

2016 ◽  
Vol 25 (12) ◽  
pp. 1650160
Author(s):  
Iqra Farhat ◽  
Muhammad Yasir Qadri ◽  
Nadia N. Qadri ◽  
Jameel Ahmed
Keyword(s):  
Fuzzy Logic ◽  
Energy Consumption ◽  
Design Space Exploration ◽  
Design Space ◽  
Multicore Architectures ◽  
L2 Cache ◽  
On Chip ◽  
L1 And L2 ◽  
The Impact ◽  
Target Design

Moore’s law has been one of the reason behind the evolution of multicore architectures. Modern multicore architectures offer great amount of parallelism and on-chip resources that remain underutilized. This is partly due to inefficient resource allocation by operating system or application being executed. Consequently the poor resource utilization results in greater energy consumption and less throughput. This paper presents a fuzzy logic-based design space exploration (DSE) approach to reconfigure a multicore architecture according to workload requirements. The target design space is explored for L1 and L2 cache size and associativity, operating frequency, and number of cores, while the impact of various configurations of these parameters is analyzed on throughput, miss ratios for L1 and L2 cache and energy consumption. MARSSx86, a cycle accurate simulator, running various SPALSH-2 benchmark applications has been used to evaluate the architecture. The proposed fuzzy logic-based DSE approach resulted in reduction in energy consumption along with an overall improved throughput of the system.

Special Issue on Networks-on-Chip and Memories for Multicore Architectures

2014 ◽  
Vol 38 (4) ◽  
pp. 253
Author(s):  
Diana Goehringer ◽  
Hamid Sarbazi-Azad ◽  
Rainer Stotzka
Keyword(s):  
Multicore Architectures ◽  
Special Issue ◽  
Networks On Chip ◽  
On Chip

scholarly journals Shared Memory Verification for Multicore Chip Designs

2021 ◽  
Author(s):  
Marleson Graf ◽  
Luiz C. V. dos Santos
Keyword(s):  
Integrated Circuits ◽  
Shared Memory ◽  
Test Generation ◽  
Computer Aided Design ◽  
General Purpose ◽  
Functional Verification ◽  
Multicore Architectures ◽  
Consistency Model ◽  
Novel Approach ◽  
On Chip

A multicore chip usually provides a shared memory abstraction implemented by a cache coherence protocol. On-chip coherence can scale gracefully as the number of cores grows, and it plays a major role for general purpose applications. Besides, multicore architectures are likely to relax constraints on store atomicity and on the ordering between loads and stores. As a result, the validation of shared memory faces two main challenges: the higher number of valid execution behaviors and the larger coherence protocol's state space. This dissertation faces those challenges and targets an important design automation phase: the (pre-silicon) functional verification of the shared memory subsystem of a multicore chip, whose behavior is specified by a memory consistency model (MCM). The main scientific contribution is a novel approach to the building of MCM checkers, along with technical contributions on random test generation and directed test generation. The contributions were reported by two papers in a premier IEEE/ACM conference and two articles in the most prestigious IEEE journal on Computer Aided Design of Integrated Circuits and Systems.

Sign in / Sign up

Export Citation Format

Share Document