A Low Power High Linearity THA for 8Bit 100Msample/s Pipeline ADC

2013 ◽  
Vol 1 (2) ◽  
pp. 44-47
Author(s):  
Xiaodan Zhou ◽  
Ai Guo ◽  
Chen Su
Author(s):  
Jae-Sik Jang ◽  
Laurence Moquillon ◽  
Patrice Garcia ◽  
Estelle Lauga-Larroze ◽  
Jean-Michel Fournier

Author(s):  
Abolfazl Ebrahimi ◽  
Mohamad Jafar Hemmati ◽  
Ahmad Hakimi ◽  
Kambiz Afrooz
Keyword(s):  

2019 ◽  
Vol 55 (24) ◽  
pp. 1273-1275 ◽  
Author(s):  
J.E. Kim ◽  
T. Yoo ◽  
K.‐H. Baek ◽  
T.T.‐H. Kim

2012 ◽  
Vol 70 (4) ◽  
pp. 1623-1632
Author(s):  
Sichun Du ◽  
Wenbin Huang ◽  
Chunhua Wang ◽  
Guangxiang Zhang ◽  
Jianguo Zhang

2019 ◽  
Vol 29 (06) ◽  
pp. 2050086 ◽  
Author(s):  
Yushi Chen ◽  
Yiqi Zhuang ◽  
Hualian Tang

An ultra-low power consumption high-linearity switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented with a mixed switching method. Based on the combination of C-2C dummy capacitors, the charge sharing technique and monotonic switching method, the proposed switching method achieves high-energy saving and high linearity. Compared with the conventional SAR ADC, the proposed method consumes no reset energy and achieves 98.9% less switching energy and 87.2% reduction in capacitor area. Moreover, the proposed scheme obtains good performance in linearity. Furthermore, the common-mode voltage variation of the proposed scheme is smaller than other published schemes, which is important for decreasing input-dependent offset of the comparator.


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