2005 IEEE Conference on Electron Devices and Solid-State Circuits
Latest Publications

TOTAL DOCUMENTS

226

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0780393392

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

UHF Surface Velocities Radar System Design

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635299 ◽

2006 ◽

Author(s):

Wen Biyang Ma Zhigang

Keyword(s):

System Design ◽

Radar System

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Realization of an Integrated Planar LC Low-Pass Filter with Modified Surface Micromachining Technology

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635379 ◽

2006 ◽

Cited By ~ 3

Author(s):

Z. W. Liu J. Fang

Keyword(s):

Surface Micromachining ◽

Pass Filter ◽

Low Pass Filter ◽

Low Pass ◽

Modified Surface

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Second Generation Current Mode Active Pixel Sensor

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635375 ◽

2006 ◽

Author(s):

A. Bermak C. K. Wah

Keyword(s):

Second Generation ◽

Current Mode ◽

Active Pixel Sensor ◽

Active Pixel

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A Full Swing And Low Power Voltage-Controlled Ring Oscillator

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635226 ◽

2006 ◽

Cited By ~ 7

Author(s):

Dunshan Yu Xin wu

Keyword(s):

Low Power ◽

Ring Oscillator ◽

Full Swing

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Opportunities and Challenges of Emerging Nanotechnologies for Future High-Speed and Low-Power Logic Applications

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635194 ◽

2006 ◽

Cited By ~ 2

Author(s):

R. Chau

Keyword(s):

Low Power ◽

High Speed ◽

Low Power Logic

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Design for Manufacturability of Sub-100 Nanometer Standard Cells

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635407 ◽

2006 ◽

Cited By ~ 1

Author(s):

Zhang Peiyong Ji Xuemei

Keyword(s):

Design For Manufacturability ◽

Standard Cells

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Methodology to Evaluate the Robustness of Integrated Circuits under Cable Discharge Event

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635317 ◽

2006 ◽

Author(s):

Ming-Dou Ker Tai-Xiang Lai

Keyword(s):

Integrated Circuits

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Gate-Misalignment-Effect Related Capacitance Behavior of a 100nm Double-Gate FD SOI NMOS Device with n>sup/supsup/sup

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635290 ◽

2006 ◽

Cited By ~ 1

Author(s):

C. H. Hsu J. B. Kuo

Keyword(s):

Double Gate ◽

Misalignment Effect ◽

Bottom Gate

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Monitoring of Switching Activity and Transition Times of Clock Signals in SoC Cells by Estimation of the Mean Value of IDD Current

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635384 ◽

2006 ◽

Author(s):

P. Dziurdzia

Keyword(s):

Mean Value ◽

Switching Activity ◽

The Mean ◽

Transition Times

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A Capped Trimming Hard-Mask Patterning Technique for Integration of Nano-Devices and Conventional Integrated Circuits

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635393 ◽

2006 ◽

Author(s):

Philip C. H. Chan Xusheng Wu

Keyword(s):

Integrated Circuits ◽

Hard Mask ◽

Patterning Technique

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2005 IEEE Conference on Electron Devices and Solid-State CircuitsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

UHF Surface Velocities Radar System Design

Realization of an Integrated Planar LC Low-Pass Filter with Modified Surface Micromachining Technology

Second Generation Current Mode Active Pixel Sensor

A Full Swing And Low Power Voltage-Controlled Ring Oscillator

Opportunities and Challenges of Emerging Nanotechnologies for Future High-Speed and Low-Power Logic Applications

Design for Manufacturability of Sub-100 Nanometer Standard Cells

Methodology to Evaluate the Robustness of Integrated Circuits under Cable Discharge Event

Gate-Misalignment-Effect Related Capacitance Behavior of a 100nm Double-Gate FD SOI NMOS Device with n>sup/supsup/sup

Monitoring of Switching Activity and Transition Times of Clock Signals in SoC Cells by Estimation of the Mean Value of IDD Current

A Capped Trimming Hard-Mask Patterning Technique for Integration of Nano-Devices and Conventional Integrated Circuits

2005 IEEE Conference on Electron Devices and Solid-State Circuits
Latest Publications