scholarly journals Reflectionless grating couplers for Silicon-on-Insulator photonic integrated circuits

2012 ◽  
Vol 20 (20) ◽  
pp. 22278 ◽  
Author(s):  
D. Vermeulen ◽  
Y. De Koninck ◽  
Y. Li ◽  
E. Lambert ◽  
W. Bogaerts ◽  
...  
Author(s):  
W. Bogaerts ◽  
S.K. Selvaraja ◽  
P. Dumon ◽  
P. Absil ◽  
D. Van Thourhout ◽  
...  

Author(s):  
Marcus S. Dahlem ◽  
Milos A. Popovic ◽  
Charles W. Holzwarth ◽  
Anatol Khilo ◽  
Tymon Barwicz ◽  
...  

2007 ◽  
Vol 19 (23) ◽  
pp. 1919-1921 ◽  
Author(s):  
Frederik Van Laere ◽  
Tom Claes ◽  
Jonathan Schrauwen ◽  
Stijn Scheerlinck ◽  
Wim Bogaerts ◽  
...  

Author(s):  
G. Roelkens ◽  
L. Liu ◽  
J. Van Campenhout ◽  
J. Brouckaert ◽  
D. Van Thourhout ◽  
...  

2004 ◽  
Vol 12 (8) ◽  
pp. 1583 ◽  
Author(s):  
W. Bogaerts ◽  
D. Taillaert ◽  
B. Luyssaert ◽  
P. Dumon ◽  
J. Van Campenhout ◽  
...  

2017 ◽  
Vol 27 (4) ◽  
pp. 327 ◽  
Author(s):  
Dung Cao Truong ◽  
Dao Anh Vu ◽  
Chung Vu Hoang

In this paper, we introduce a new two-mode (de)multiplexer based on the silicon-on-insulator (SOI) platform. The device is built on a symmetric Y-junction, a 2×2 multimode interference (MMI) waveguide and a phaseshifter in the form of a ridge waveguide which is designed using 3D scalar beam propagation method (BPM). The phase evolution in the structure is discussed in details. Simulation results show that the device can operate in a wide wavelength range (150 nm) with a low insertion loss and small crosstalk. Large fabrication tolerance to the width of the input waveguide up to 100 nm is achieved, which is compatible to the current CMOS manufacturing technologies for the photonic integrated circuits. Furthermore, the small footprint (4µm×286µm) makes the device suitable for applications in high bitrate and compact on-chip silicon photonic integrated circuits.


2018 ◽  
Vol 8 (7) ◽  
pp. 1142 ◽  
Author(s):  
Siddharth Nambiar ◽  
Purnima Sethi ◽  
Shankar Selvaraja

Fiber to chip coupling is a critical aspect of any integrated photonic circuit. In terms of ease of fabrication as well as wafer-scale testability, surface grating couplers are by far the most preferred scheme of the coupling to integrated circuits. In the past decade, considerable effort has been made for designing efficient grating couplers on Silicon-on-Insulator (SOI) and other allied photonic platforms. Highly efficient grating couplers with sub-dB coupling performance have now been demonstrated. In this article, we review the recent advances made to develop grating coupler designs for a variety of applications on SOI platform. We begin with a basic overview of design methodology involving both shallow etched gratings and the emerging field of subwavelength gratings. The feasibility of reducing footprint by way of incorporating compact tapers is also explored. We also discuss novel grating designs like polarization diversity as well as dual band couplers. Lastly, a brief description of various packaging and wafer-scale testing schemes available for fiber-chip couplers is elaborated.


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