Grating-Assisted Fiber to Chip Coupling for SOI Photonic Circuits

Fiber to chip coupling is a critical aspect of any integrated photonic circuit. In terms of ease of fabrication as well as wafer-scale testability, surface grating couplers are by far the most preferred scheme of the coupling to integrated circuits. In the past decade, considerable effort has been made for designing efficient grating couplers on Silicon-on-Insulator (SOI) and other allied photonic platforms. Highly efficient grating couplers with sub-dB coupling performance have now been demonstrated. In this article, we review the recent advances made to develop grating coupler designs for a variety of applications on SOI platform. We begin with a basic overview of design methodology involving both shallow etched gratings and the emerging field of subwavelength gratings. The feasibility of reducing footprint by way of incorporating compact tapers is also explored. We also discuss novel grating designs like polarization diversity as well as dual band couplers. Lastly, a brief description of various packaging and wafer-scale testing schemes available for fiber-chip couplers is elaborated.

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Compact Focusing Grating Couplers for Silicon-on-Insulator Integrated Circuits

IEEE Photonics Technology Letters ◽

10.1109/lpt.2007.908762 ◽

2007 ◽

Vol 19 (23) ◽

pp. 1919-1921 ◽

Cited By ~ 165

Author(s):

Frederik Van Laere ◽

Tom Claes ◽

Jonathan Schrauwen ◽

Stijn Scheerlinck ◽

Wim Bogaerts ◽

...

Keyword(s):

Integrated Circuits ◽

Silicon On Insulator ◽

Grating Couplers

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Erasable diffractive grating couplers in silicon on insulator for wafer scale testing

10.1117/12.2039179 ◽

2014 ◽

Cited By ~ 1

Author(s):

R. Topley ◽

G. Martinez-Jimenez ◽

L. O'Faolain ◽

N. Healy ◽

S. Mailis ◽

...

Keyword(s):

Silicon On Insulator ◽

Grating Couplers ◽

Wafer Scale

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Reflectionless grating couplers for Silicon-on-Insulator photonic integrated circuits

Optics Express ◽

10.1364/oe.20.022278 ◽

2012 ◽

Vol 20 (20) ◽

pp. 22278 ◽

Cited By ~ 41

Author(s):

D. Vermeulen ◽

Y. De Koninck ◽

Y. Li ◽

E. Lambert ◽

W. Bogaerts ◽

...

Keyword(s):

Integrated Circuits ◽

Photonic Integrated Circuits ◽

Silicon On Insulator ◽

Grating Couplers

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Structural changes in silicon-on-insulator material during post-implantation annealing

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100145054 ◽

1986 ◽

Vol 44 ◽

pp. 736-737

Author(s):

C. O. Jung ◽

S. J. Krause ◽

S.R. Wilson

Keyword(s):

Integrated Circuits ◽

Oxide Layer ◽

High Speed ◽

Structural Changes ◽

Device Fabrication ◽

Silicon On Insulator ◽

High Quality ◽

Radiation Hardened ◽

Post Implantation ◽

Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

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Automated Detection of Pin Defects on Counterfeit Microelectronics

10.31399/asm.cp.istfa2018p0057 ◽

2018 ◽

Author(s):

Pallabi Ghosh ◽

Domenic Forte ◽

Damon L. Woodard ◽

Rajat Subhra Chakraborty

Keyword(s):

Integrated Circuits ◽

Depth Map ◽

Optical Microscope ◽

Automated Detection ◽

Detection Methods ◽

Global Supply Chains ◽

Subject Matter Experts ◽

Security Breaches ◽

The Past ◽

Skilled Subject

Abstract Counterfeit electronics constitute a fast-growing threat to global supply chains as well as national security. With rapid globalization, the supply chain is growing more and more complex with components coming from a diverse set of suppliers. Counterfeiters are taking advantage of this complexity and replacing original parts with fake ones. Moreover, counterfeit integrated circuits (ICs) may contain circuit modifications that cause security breaches. Out of all types of counterfeit ICs, recycled and remarked ICs are the most common. Over the past few years, a plethora of counterfeit IC detection methods have been created; however, most of these methods are manual and require highly-skilled subject matter experts (SME). In this paper, an automated bent and corroded pin detection methodology using image processing is proposed to identify recycled ICs. Here, depth map of images acquired using an optical microscope are used to detect bent pins, and segmented side view pin images are used to detect corroded pins.

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Fluorocarbon Precursor for High Aspect Ratio via Milling in Focused Ion Beam Modification of Integrated Circuits

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2004p0534 ◽

2004 ◽

Author(s):

Valery Ray

Keyword(s):

Side Effects ◽

Aspect Ratio ◽

Integrated Circuits ◽

High Aspect Ratio ◽

Focused Ion Beam ◽

Ion Beam ◽

Enabling Technology ◽

Si Substrate ◽

Ion Beam Modification ◽

The Past

Abstract Gas Assisted Etching (GAE) is the enabling technology for High Aspect Ratio (HAR) circuit access via milling in Focused Ion Beam (FIB) circuit modification. Metal interconnect layers of microelectronic Integrated Circuits (ICs) are separated by Inter-Layer Dielectric (ILD) materials, therefore HAR vias are typically milled in dielectrics. Most of the etching precursor gases presently available for GAE of dielectrics on commercial FIB systems, such as XeF2, Cl2, etc., are also effective etch enhancers for either Si, or/and some of the metals used in ICs. Therefore use of these precursors for via milling in dielectrics may lead to unwanted side effects, especially in a backside circuit edit approach. Making contacts to the polysilicon lines with traditional GAE precursors could also be difficult, if not impossible. Some of these precursors have a tendency to produce isotropic vias, especially in Si. It has been proposed in the past to use fluorocarbon gases as precursors for the FIB milling of dielectrics. Preliminary experimental evaluation of Trifluoroacetic (Perfluoroacetic) Acid (TFA, CF3COOH) as a possible etching precursor for the HAR via milling in the application to FIB modification of ICs demonstrated that highly enhanced anisotropic milling of SiO2 in HAR vias is possible. A via with 9:1 aspect ratio was milled with accurate endpoint on Si and without apparent damage to the underlying Si substrate.

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ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1998p0235 ◽

1998 ◽

Author(s):

D.S. Patrick ◽

L.C. Wagner ◽

P.T. Nguyen

Keyword(s):

Integrated Circuits ◽

Failure Analysis ◽

Yield Enhancement ◽

Production Test ◽

Final Test ◽

Critical Design ◽

The Past ◽

Product Engineering ◽

Time Savings ◽

Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

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An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors

ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2005p0457 ◽

2005 ◽

Author(s):

Pei Y. Tsai ◽

Junedong Lee ◽

Paul Ronsheim ◽

Lindsay Burns ◽

Richard Murphy ◽

...

Keyword(s):

Integrated Circuits ◽

Device Fabrication ◽

Sampling Plan ◽

Silicon On Insulator ◽

Manufacturing Processes ◽

Circuit Performance ◽

Characterization Techniques ◽

Wafer Manufacturing

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

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