scholarly journals Low Power Area-Efficient Adiabatic Vedic Multiplier

2014 ◽  
Vol 03 (08) ◽  
pp. 11027-11032
Author(s):  
K. Narendra ◽  
Sagara Pandu
Keyword(s):  
Low Power ◽  
Vedic Multiplier ◽  
Area Efficient

scholarly journals Implementation of Low Power and Area Efficient Vedic Multiplier

2019 ◽  
Vol 9 (1S) ◽  
pp. 206-209 ◽  
Keyword(s):  
Power Consumption ◽  
Comparative Study ◽  
Low Power ◽  
Full Adder ◽  
Layout Design ◽  
Performance Parameters ◽  
Vedic Multiplier ◽  
Area Efficient

Designing a low power consuming and area efficient Vedic Multiplier using Hybrid Full Adder. In this paper, Conventional CMOS (CCMOS) Full Adders involved in a conventional Vedic multiplier is replaced with Hybrid Full adders to achieve reduction in power consumption and area. In the proposed system ripple carry adders involved in Vedic multiplier are designed using Hybrid Full Adder. The design is done for 2-bit and it is extrapolated to 16-bit. Performance parameters such as power consumed and area between Vedic multiplier involving CCMOS and Hybrid Full Adder is done and a comparative study over them is made. Significant improvement is achieved in this implementation and the layout design is also implemented for the 2-bit, 4-bit, 8-bit and 16-bit Vedic multiplier for both Conventional CMOS and Hybrid Full-Adder logic styles. The implementation is carried out using Tanner EDA tool under 250-nm technology.

Low-Power and Area-Efficient Approximate Parallel Design Using Bypassing

2019 ◽  
Author(s):  
Anushka Prakash B ◽  
Noah Kiran Nandi ◽  
Marimuthu R ◽  
Balamurugan S ◽  
Duraivel A.N.
Keyword(s):  
Low Power ◽  
Parallel Design ◽  
Area Efficient

Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM

2014 ◽  
Vol 573 ◽  
pp. 176-180
Author(s):  
G. Kavitha ◽  
B. Kirthiga ◽  
N. Kirubanandasarathy
Keyword(s):  
Low Power ◽  
Orthogonal Frequency Division Multiplexing ◽  
Ofdm System ◽  
Description Language ◽  
Fft Processor ◽  
Synthesis Tool ◽  
Mimo Ofdm ◽  
Hardware Description ◽  
Fft Algorithms ◽  
Area Efficient

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.

Low-power 200-Msps, area-efficient, five-tap programmable FIR filter [in BiCMOS]

1998 ◽  
Vol 33 (7) ◽  
pp. 1134-1138 ◽  
Author(s):  
D. Moloney ◽  
J. O'Brien ◽  
E. O'Rourke ◽  
F. Brianti
Keyword(s):  
Low Power ◽  
Fir Filter ◽  
Area Efficient
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