scholarly journals An Approach to the Construction of a Network Processing Unit

2019 ◽  
Vol 26 (1) ◽  
pp. 39-62
Author(s):  
Stanislav O. Bezzubtsev ◽  
Vyacheslav V. Vasin ◽  
Dmitry Yu. Volkanov ◽  
Shynar R. Zhailauova ◽  
Vladislav A. Miroshnik ◽  
...  
Keyword(s):  
Simulation Model ◽  
General Purpose ◽  
Network Processor ◽  
Processing Unit ◽  
Use Case ◽  
General Purpose Processor ◽  
Software Products ◽  
Processor Architectures ◽  
Advantages And Disadvantages ◽  
Processor Unit

The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages and disadvantages of two different versions of network processor architectures are considered: pipeline-based architecture, the stages of which are represented by a set of general-purpose processor cores, and pipeline-based architecture whose stages correspond to cores specialized for specific packet processing operations. Based on a dedicated set of the most common use case scenarios, a new architecture of the network processor unit (NPU) with functionally specialized pipeline stages was proposed. The article presents a description of the simulation model of the NPU of the proposed architecture. The simulation model of the network processor is implemented in C ++ languages using SystemC, the open-source C++ library. For the functional testing of the obtained NPU model, the described use case scenarios were implemented in C. In order to evaluate the performance of the proposed NPU architecture a set of software products developed by KM211 company and the KMX32 family of microcontrollers were used. Evaluation of NPU performance was made on the basis of a simulation model. Estimates of the processing time of one packet and the average throughput of the NPU model for each scenario are obtained.

scholarly journals Design of an FPGA Hardware Optimizing the Performance and Power Consumption of a Plenoptic Camera Depth Estimation Algorithm

Algorithms ◽  
2021 ◽  
Vol 14 (7) ◽  
pp. 215
Author(s):  
Faraz Bhatti ◽  
Thomas Greiner
Keyword(s):  
Power Consumption ◽  
Graphics Processing Unit ◽  
Depth Estimation ◽  
Estimation Algorithm ◽  
General Purpose ◽  
Processing Unit ◽  
General Purpose Processor ◽  
Plenoptic Camera ◽  
Graphics Processing ◽  
Efficient Memory

Plenoptic camera based system captures the light-field that can be exploited to estimate the 3D depth of the scene. This process generally consists of a significant number of recurrent operations, and thus requires high computation power. General purpose processor based system, due to its sequential architecture, consequently results in the problem of large execution time. A desktop graphics processing unit (GPU) can be employed to resolve this problem. However, it is an expensive solution with respect to power consumption and therefore cannot be used in mobile applications with low energy requirements. In this paper, we propose a modified plenoptic depth estimation algorithm that works on a single frame recorded by the camera and respective FPGA based hardware design. For this purpose, the algorithm is modified for parallelization and pipelining. In combination with efficient memory access, the results show good performance and lower power consumption compared to other systems.

High-performance computer graphics technologies in engineering applications

2019 ◽  
Vol 16 (2) ◽  
pp. 304-308
Author(s):  
Chao Peng
Keyword(s):  
Computer Graphics ◽  
High Performance ◽  
Graphics Processing Unit ◽  
General Purpose ◽  
Processing Unit ◽  
Data Streaming ◽  
Engineering Applications ◽  
Content Type ◽  
Central Processing ◽  
Advantages And Disadvantages

Purpose The purpose of this paper is to investigate possibilities to adopt state-of-the-art computer graphics technologies for big data visualization in engineering applications. Toward this purpose, a conceptual heterogeneous system is proposed for graphical rendering, which is established with multiple central processing unit cores and multiple graphics processing unit GPUs. Design/methodology/approach The design of the system supports both general-purpose computation and graphics-related computation. Three processing components are discussed to fulfill the execution requirements in load balancing, data streaming and display. This design fully uses computational and memory resources and enhances the performance with the support of GPU-based parallelization. Findings The advantages and disadvantages of particular technical methods for each processing component are discussed. The possible ways to integrate them are analyzed. Originality/value This work has contributions of using computer graphics technologies in engineering applications.

Design and Implementation of Low Energy Wireless Network Nodes based on Hardware Compression Acceleration

2019 ◽  
Vol 12 ◽  
Author(s):  
Hui Yang ◽  
Anand Nayyar
Keyword(s):  
Energy Consumption ◽  
Data Compression ◽  
Energy Saving ◽  
Optimization Design ◽  
Hardware Acceleration ◽  
Transmission Efficiency ◽  
General Purpose ◽  
Storage Space ◽  
General Purpose Processor ◽  
Compression Time

: In the fast development of information, the information data is increasing in geometric multiples, and the speed of information transmission and storage space are required to be higher. In order to reduce the use of storage space and further improve the transmission efficiency of data, data need to be compressed. processing. In the process of data compression, it is very important to ensure the lossless nature of data, and lossless data compression algorithms appear. The gradual optimization design of the algorithm can often achieve the energy-saving optimization of data compression. Similarly, The effect of energy saving can also be obtained by improving the hardware structure of node. In this paper, a new structure is designed for sensor node, which adopts hardware acceleration, and the data compression module is separated from the node microprocessor.On the basis of the ASIC design of the algorithm, by introducing hardware acceleration, the energy consumption of the compressed data was successfully reduced, and the proportion of energy consumption and compression time saved by the general-purpose processor was as high as 98.4 % and 95.8 %, respectively. It greatly reduces the compression time and energy consumption.

CPU AND GPU PERFORMANCE ANALYSIS ON 2D MATRIX OPERATION

2021 ◽  
Vol 2 (1) ◽  
pp. 1
Author(s):  
Kwek Benny Kurniawan ◽  
YB Dwi Setianto
Keyword(s):  
Graphic Processing Unit ◽  
Computing Time ◽  
General Purpose ◽  
Parallel Processors ◽  
Processing Unit ◽  
Matrix Operation ◽  
Industry Standard ◽  
Programming Interfaces ◽  
Complete Matrix ◽  
Matrix Calculation

GPU or Graphic Processing Unit can be used on many platforms in general GPUs are used for rendering graphics but now GPUs are general purpose parallel processors with support for easily accessible programming interfaces and industry standard languages such as C, Python and Fortran. In this study, the authors will compare CPU and GPU for completing some matrix calculation. To compare between CPU and GPU, the authors have done some testing to observe the use of Processing Unit, memory and computing time to complete matrix calculations by changing matrix sizes and dimensions. The results of tests that have been done shows asynchronous GPU is faster than sequential. Furthermore, thread for GPU needs to be adjusted to achieve efficiency in GPU load.

Sign in / Sign up

Export Citation Format

Share Document