Means and Methods of Efficiency Estimation of Video Stream Transmission Based on GigE Vision Technology Using Application Processor

The paper investigates the possibility of efficient implementation of a GigE Vision compatible video stream source on a computing platform based on a system-on-a-chip with general-purpose ARM processor cores. In particular, to implement the aforementioned video source, a proprietary prototype of a GigE Vision compatible camera was developed based on the Raspberry Pi 4 single-board computer. This computing platform was chosen due to its widespread use and wide community support. The software part of the camera is implemented using the Video4Linux and Aravis libraries. The first library is used for the primary image capturing from a video sensor connected to a single board computer. The second library is intended for forming and transmission of video stream frames compatible with GigE Vision technology over the network. To estimate the delays in the transmission of a video stream over an Ethernet channel, a methodology based on the Precise Time Protocol (PTP) has been proposed and applied. During the experiments, it was found that the software implementation of a GigE Vision compatible camera on single-board computers with general-purpose processor cores is quite promising. Without additional optimization, such an implementation can be successfully used to transmit small frames (with a resolution of up to 640 × 480 pixels), giving a delay less than 10 ms. At the same time, some additional optimizations may be required to transmit larger frames. Namely, a MTU (maximum transmission unit) size value plays the crucial role in latency formation. Thus, to implement a faster camera, it is necessary to select a platform that supports the largest possible MTU (unfortunately, it turned out that it is not possible with Raspberry Pi 4, as it supports relatively small MTU size of up to 2000 bytes). In addition, the image format conversion procedure can noticeably affect the delay. Therefore, it is highly desirable to avoid any frame processing on the transmitter side and, if it is possible, to broadcast raw images. If the conversion of the frame format is necessary, the platform should be chosen so that there are free computing cores on it, which will permit to distribute all necessary frame conversions between these cores using parallelization techniques.

SoC-FPGA systems for the acquisition and processing of electroencephalographic signals

<span lang="EN-US">Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.</span>

A Manycore Vision Processor for Real-Time Smart Cameras

Real-time image processing and computer vision systems are now in the mainstream of technologies enabling applications for cyber-physical systems, Internet of Things, augmented reality, and Industry 4.0. These applications bring the need for Smart Cameras for local real-time processing of images and videos. However, the massive amount of data to be processed within short deadlines cannot be handled by most commercial cameras. In this work, we show the design and implementation of a manycore vision processor architecture to be used in Smart Cameras. With massive parallelism exploration and application-specific characteristics, our architecture is composed of distributed processing elements and memories connected through a Network-on-Chip. The architecture was implemented as an FPGA overlay, focusing on optimized hardware utilization. The parameterized architecture was characterized by its hardware occupation, maximum operating frequency, and processing frame rate. Different configurations ranging from one to eighty-one processing elements were implemented and compared to several works from the literature. Using a System-on-Chip composed of an FPGA integrated into a general-purpose processor, we showcase the flexibility and efficiency of the hardware/software architecture. The results show that the proposed architecture successfully allies programmability and performance, being a suitable alternative for future Smart Cameras.

Design of an FPGA Hardware Optimizing the Performance and Power Consumption of a Plenoptic Camera Depth Estimation Algorithm

Plenoptic camera based system captures the light-field that can be exploited to estimate the 3D depth of the scene. This process generally consists of a significant number of recurrent operations, and thus requires high computation power. General purpose processor based system, due to its sequential architecture, consequently results in the problem of large execution time. A desktop graphics processing unit (GPU) can be employed to resolve this problem. However, it is an expensive solution with respect to power consumption and therefore cannot be used in mobile applications with low energy requirements. In this paper, we propose a modified plenoptic depth estimation algorithm that works on a single frame recorded by the camera and respective FPGA based hardware design. For this purpose, the algorithm is modified for parallelization and pipelining. In combination with efficient memory access, the results show good performance and lower power consumption compared to other systems.

Reduction of Power in General Purpose Processor Through Clock-Gating Technique

Now a days DC power supply plays very important role in the Electronic industry because for every electronic gadget DC power is required to operate it. Even though durable DC batteries are available in the market to operate the various electronic gadgets for more time, electronic designers are continuously concentrating more and more to reduce the power through the various new Technologies like increasing parallel operations, pipe line concepts [1] etc. To work such durable batteries more duration than the actual duration what they can give, in this work we are concentrating on the 'clock-gating' technique to reduce the power in the general purpose microprocessor. For every microprocessor clock is required. All operations of any processor are performed by the clock cycle. There are various blocks in the processor but all the blocks are not operated at a time while using it, some blocks in the off mode while other blocks are in the working mode. Hence in order to power off such blocks for a little while clock gating is used in this work. Wherever particular block is not operated, for that block clock is disabled by the clock gating technique. The main principle of clock getting is nothing but ANDing the processor clock with a gate-control signal.

A Dynamic and Highly Configurable Crypto-Processor for brief communication interval

In modern computing systems data security is of paramount importance. The data transfer must be made secure because it can be significantly sensitive for any organization involved. This paper expounds a SOC architecture to facilitate end to end secure data exchange for applications involving short communication intervals. This SOC has been designed to behave as a co-processor which along with a standard general-purpose processor would serve as a cryptosystem. The SOC employs two famous algorithms – RSA and AES for cryptography. In contrast to usual single key cryptographic systems, this paper tries to elaborate an innovative methodology involving dynamic security measures that makes the system distributed rather than making it central to a specific algorithm and hence a particular key. The methodology involves generating and using an AES key for data encryption and RSA key for secure transfer of the AES key between the point of transmission and reception.

Complexity Analysis of a Versatile Video Coding Decoder over Embedded Systems and General Purpose Processors

The increase in high-quality video consumption requires increasingly efficient video coding algorithms. Versatile video coding (VVC) is the current state-of-the-art video coding standard. Compared to the previous video standard, high efficiency video coding (HEVC), VVC demands approximately 50% higher video compression while maintaining the same quality and significantly increasing the computational complexity. In this study, coarse-grain profiling of a VVC decoder over two different platforms was performed: One platform was based on a high-performance general purpose processor (HGPP), and the other platform was based on an embedded general purpose processor (EGPP). For the most intensive computational modules, fine-grain profiling was also performed. The results allowed the identification of the most intensive computational modules necessary to carry out subsequent acceleration processes. Additionally, the correlation between the performance of each module on both platforms was determined to identify the influence of the hardware architecture.

Smart Fast Motion Estimation Processors

This Paper displays an adaptable and versatile movement estimation processor fit for supporting the handling prerequisites for top notch (HD) video utilizing the H.264 Advanced Video Codec, which is appropriate for FPGA execution. This paper dependent on General Purpose processor plan for movement estimation process. Quick movement estimation calculation with full pursuit calculation and precious stone hunt calculation. Where the two calculations have been executed in a solitary processor. So client can powerfully pick as per best execution. A client can choose the alternative of video quality at run time. In contrast to most past work, our center is enhanced to execute all current quick square coordinating calculations, to coordinate or surpass the between casing expectation execution of full-seek approaches at the HD goals generally being used today. Different tale movement estimation designs have been proposed all through the writing for dealing with the high data transfer capacity imperative nature of Video Broadcasting. A High precision full pursuit fixed square inquiry calculation is used to lessen the general transmission capacity and power prerequisite for transmitting live video arrangements. Despite the fact that full hunt guarantees high exactness, it tradeoffs its calculation time for precision. So the precision advantage is emphatically obscured by working velocity. To supplant the Full inquiry calculation another Modified Diamond seek calculation has been proposed with best precision and streamlined movement estimation length. Execution assessment of FBS Full hunt and Diamond look will be thought about for future investigation