scholarly journals Responsive Multithreaded Processor for Distributed Real-Time Systems

2005 ◽  
Vol 17 (2) ◽  
pp. 130-141 ◽  
Author(s):  
Nobuyuki Yamasaki ◽  
Keyword(s):  
Real Time ◽  
Design Rule ◽  
Processing Unit ◽  
Real Time Systems ◽  
Real Time Processing ◽  
Vector Operation ◽  
Lower Priority ◽  
Functional Units ◽  
On Chip ◽  
Time Systems

The Responsive MultiThreaded (RMT) Processor is a system LSI that integrates almost all functions for parallel/distributed real-time systems including robots, intelligent rooms/buildings, ubiquitous computing systems, and amusement systems. Concretely, the RMT Processor integrates real-time processing (RMT Processing Unit), real-time communication (Responsive Link II), computer I/O peripherals (DDR SDRAM I/Fs, DMAC, PCI-X, USB2.0, IEEE1394, etc.), and control I/O peripherals (PWM generators, pulse counters, etc.). The RMT Processor, with a design rule of 0.13<I>μ</I>m CMOS Cu 1P8M and a die size 10.0mm square, was fabricated by TSMC. The RMT Processing Unit (RMT PU) executes eight prioritized threads simultaneously using fine-grained multithreading based on priority, called the RMT architecture. Priority of real-time systems is introduced into all functional units, including cache, fetch, and execution, so the RMT PU guarantees real-time execution of prioritized threads. If resource conflicts occur at functional units, higher priority threads overtake lower priority threads. Flexible powerful vector operation units for multimedia processing are also designed. System designers use on-chip functions easily by connecting required I/Os to this chip and the designers realize distributed control by connecting several RMT Processors with their own functions via Responsive Link II.

Global Fixed Priority Scheduling with Constructing Execution Dependency in Multiprocessor Real-Time Systems

2018 ◽  
Vol 27 (10) ◽  
pp. 1850165
Author(s):  
Meiling Han ◽  
Tianyu Zhang ◽  
Yuhan Lin ◽  
Zhiwei Feng ◽  
Qingxu Deng
Keyword(s):  
Real Time ◽  
Real Time Systems ◽  
Analysis Method ◽  
Priority Scheduling ◽  
Fixed Priority ◽  
Fixed Priority Scheduling ◽  
Lower Priority ◽  
Acceptance Ratio ◽  
Processor Performance ◽  
Time Systems

The increasing demands for processor performance are driving system designers to adopt multiprocessors. In this paper, we study global fixed priority scheduling in multiprocessor real-time systems and introduce a technique for improving the schedulability. The key idea is to construct execution dependency for selected tasks to leverage slack time and reduce the interference between high-priority and low-priority tasks. Thus, more lower-priority tasks are enabled to be scheduled. Further, we provide a response time analysis method which takes the execution constraint of tasks into consideration. Extensive simulation results indicate that the proposed approach outperforms existing work in terms of acceptance ratio.

Self-Aware Network-on-Chip Control in Real-Time Systems

2018 ◽  
Vol 35 (5) ◽  
pp. 19-27 ◽  
Author(s):  
Adam Kostrzewa ◽  
Sebastian Tobuschat ◽  
Rolf Ernst
Keyword(s):  
Real Time ◽  
Network On Chip ◽  
Real Time Systems ◽  
On Chip ◽  
Time Systems

Design Concept of Responsive Multithreaded Processor for Distributed Real-Time Control

2004 ◽  
Vol 16 (2) ◽  
pp. 194-199 ◽  
Author(s):  
Nobuyuki Yamasaki ◽  
Keyword(s):  
Real Time ◽  
Design Concept ◽  
Processing Unit ◽  
Home Automation ◽  
Real Time Control ◽  
Real Time Processing ◽  
Time Control ◽  
Multithreaded Processor ◽  
On Chip ◽  
Asic Chip

This paper describes the design concept of Responsive MultiThreaded (RMT) Processor for distributed real-time control that controls various embedded systems including robots, home automation, factory automation, etc. RMT processor integrates an 8-way multithreaded processor (RMT processing unit) for real-time processing, four sets of Responsive Link II for real-time communication, and I/O peripherals including DDR SDRAM I/Fs, DMAC, PCI64, USB2.0, IEEE1394, PWM generators, pulse counters, etc., into an ASIC chip. System designers can use various on-chip functions easily by connecting required I/Os to this chip directly. The designers can also realize distributed control systems by connecting several RMT processors with their own functions via Responsive Link II.

scholarly journals On-chip ring network designs for hard-real time systems

2013 ◽  
Author(s):  
Miloš Panić ◽  
German Rodriguez ◽  
Eduardo Quiñones ◽  
Jaume Abella ◽  
Francisco J. Cazorla
Keyword(s):  
Real Time ◽  
Real Time Systems ◽  
Ring Network ◽  
On Chip ◽  
Hard Real Time ◽  
Time Systems

scholarly journals DESIGN & DEVELOPMENT OF REAL-TIME MULTITASKING MICROKERNEL BASED ON ARM7TDMI FOR INDUSTRIAL AUTOMATION

2012 ◽  
pp. 68-71
Author(s):  
SHAKTIRAJ KUMAR CHAGANTY ◽  
B. LAVAN ◽  
DR.S.SIVA PRASAD
Keyword(s):  
Operating System ◽  
Real Time ◽  
Research Work ◽  
Processing Unit ◽  
Real Time Systems ◽  
Design Development ◽  
Central Processing ◽  
Context Switching ◽  
Time Systems ◽  
Work First

A real-time microkernel is the near-minimum amount of software that can provide the mechanisms needed to implement a real-time operating system. Real-time systems are those systems whose response is deterministic in time. In our research a 32-task Real Time Microkernel is designed using which multi tasking can be done on the targeted processor ARM7TDMI. Two sets of functions are developed in this research work. First one is Operating System functions and second is application functions. Operating System functions are mainly for carrying out task creation, multi-tasking, scheduling, context switching and Inter task communication. The process of scheduling and switching the CPU (Central Processing Unit) between several tasks is illustrated in this paper. The number of application functions can vary between 1 to 32. Each of these application functions is created as a task by the microkernel and scheduled by the pre-emptive priority scheduler. Multi tasking of these application tasks is demonstrated in this paper.

A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems

2019 ◽  
Vol 28 (supp01) ◽  
pp. 1940005 ◽  
Author(s):  
Lukáš Kohútka ◽  
Lukáš Nagy ◽  
Viera Stopjaková
Keyword(s):  
Real Time ◽  
Real Time Systems ◽  
Chip Area ◽  
Hardware Architectures ◽  
On Chip ◽  
Hard Real Time ◽  
Time Systems ◽  
Earliest Deadline ◽  
Novel Design ◽  
Mixed Criticality

This paper presents a novel design of a coprocessor that performs hardware-accelerated task scheduling for embedded real-time systems consisting of mixed-criticality real-time tasks. The proposed solution is based on the Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time tasks. Thanks to the HW implementation of the scheduler in the form of a coprocessor, the scheduler operations (i.e., instructions) are always completed in two clock cycles regardless of the actual or even maximum task amount within the system. The proposed scheduler was verified using simplified version of UVM and applying billions of randomly generated instructions as inputs to the scheduler. Chip area costs are evaluated by synthesis for Intel FPGA Cyclone V and for 28-nm TSMC ASIC. Three versions of real-time task schedulers were compared: EDF-based scheduler designed for hard real-time tasks only, GED-based scheduler and the proposed RED-based scheduler, which is suitable for tasks of various criticalities. According to the synthesis results, the RED-based scheduler consumes LUTs and occupies larger chip area than the original EDF-based scheduler with equivalent parameters used. However, the RED-based scheduler handles variations of task execution times better, achieves higher CPU utilization and can be used for the scheduling of hard real-time, soft real-time and nonreal-time tasks combined in one system, which is not possible with the former algorithms.

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