Enhance the Performance of Associative Memory by Using New Methods

2017 ◽  
pp. 49-56
Author(s):  
◽  
Keyword(s):  
Associative Memory ◽  
Memory Performance ◽  
Cache Memory ◽  
Access Time ◽  
Multicore Processor ◽  
Cache Performance ◽  
New Methods ◽  
Cache Access ◽  
Multiple Tasks ◽  
Performance Evaluating

Data or instructions that are regularly used are saved in cache so that it is very easy to retrieve for the purpose of increase the cache performance. Evaluating the execution of multi-core systems the part of the cache memory is very important. A multicore processor is shared circuit in which two or more processors are joined to enhance the performance and perform multiple tasks. This paper describes the performance of cache memory based on cache access time, miss rate and miss penalty. Cache mapping methods are defined to increase the performance of cache but it face many difficulties. Some methods and algorithms are used to decrease these difficulties. In this paper describes the study of recent competing processors to evaluate the cache memory performance.

ASYNCHRONOUS INSTRUCTION CACHE MEMORY FOR AVERAGE-CASE PERFORMANCE

2014 ◽  
Vol 23 (05) ◽  
pp. 1450063 ◽  
Author(s):  
JE-HOON LEE ◽  
HYUN GUG CHO
Keyword(s):  
Cache Memory ◽  
Access Time ◽  
Cmos Process ◽  
Worst Case ◽  
Average Case ◽  
Instruction Cache ◽  
Segmentation Technique ◽  
Asynchronous Instruction ◽  
Cache Access ◽  
Number Of Segments

This paper presents an asynchronous instruction cache memory for average-case performance, rather than worst-case performance. Even though the proposed instruction cache design is based on a fixed delay model, it can achieve high throughput by employing a new memory segmentation technique that divides cache memory cell arrays into multiple memory segments. The conventional bit-line memory segmentation divides a whole memory system into multiple segments so that all memory segments have the same size. On the contrary, we propose a new bit-line segmentation technique for the cache memory which consists of multiple segments but all the memory segments have the same delay bound for themselves. We use the resister-capacitor (R-C) modeling of bit-line delay for content addressable memory–random access memory (CAM–RAM) structure in a cache in order to estimate the total bit-line delay. Then, we decide the number of segments to trade-off between the throughput and complexity of a cache system. We synthesized a 128 KB cache memory consisting of various segments from 1 to 16 using Hynix 0.35-μm CMOS process. From the simulation results, our implementation with dividing factor 4 and 16 can reduce the average cache access time to 28% and 35% when compared to the non-segmented counterpart system. It also shows that our implementation can reduce the average cache access time by 11% and 17% when compared to the bit-line segmented cache that consists of the same number of segments that have the same size.

Improving of cache memory performance based on a fuzzy clustering based page replacement algorithm by using four features

2020 ◽  
Vol 39 (5) ◽  
pp. 7899-7908
Author(s):  
Davood Akbari-Bengar ◽  
Ali Ebrahimnejad ◽  
Homayun Motameni ◽  
Mehdi Golsorkhtabaramiri
Keyword(s):  
Fuzzy Clustering ◽  
High Speed ◽  
Human Life ◽  
Memory Performance ◽  
Cache Memory ◽  
Access Time ◽  
Data Sets ◽  
Network Bandwidth ◽  
Replacement Algorithm ◽  
Use Of The Internet

Internet is one of the most influential new communication technologies has influenced all aspects of human life. Extensive use of the Internet and the rapid growth of network services have increased network traffic and ultimately a slowdown in internet speeds around the world. Such traffic causes reduced network bandwidth, server response latency, and increased access time to web documents. Cache memory is used to improve CPU performance and reduce response time. Due to the cost and limited size of cache compared to other devices that store information, an alternative policy is used to select and extract a page to make space for new pages when the cache is filled. Many algorithms have been introduced which performance depends on a high-speed web cache, but it is not well optimized. The general feature of most of them is that they are developed from the famous LRU and LFU designs and take advantage of both designs. In this research, a page replacement algorithm called FCPRA (Fuzzy Clustering based Page Replacement Algorithm) is presented, which is based on four features. When the cache space can’t respond to a request for a new page, it selects a page of the lowest priority cluster and the largest login order; then, removes it from the cache memory. The results show that FCPRA has a better hit rate with different data sets and can improve the cache memory performance compared to other algorithms.

scholarly journals The Role of Visual Association Cortex in Associative Memory Formation across Development

2018 ◽  
Vol 30 (3) ◽  
pp. 365-380 ◽  
Author(s):  
Maya L. Rosen ◽  
Margaret A. Sheridan ◽  
Kelly A. Sambrook ◽  
Matthew R. Peverill ◽  
Andrew N. Meltzoff ◽  
...  
Keyword(s):  
Associative Memory ◽  
Visual Processing ◽  
Memory Performance ◽  
Neural Mechanism ◽  
Association Cortex ◽  
Associative Memories ◽  
Associate Learning ◽  
Visual Association Cortex ◽  
Age Related

Associative learning underlies the formation of new episodic memories. Associative memory improves across development, and this age-related improvement is supported by the development of the hippocampus and pFC. Recent work, however, additionally suggests a role for visual association cortex in the formation of associative memories. This study investigated the role of category-preferential visual processing regions in associative memory across development using a paired associate learning task in a sample of 56 youths (age 6–19 years). Participants were asked to bind an emotional face with an object while undergoing fMRI scanning. Outside the scanner, participants completed a memory test. We first investigated age-related changes in neural recruitment and found linear age-related increases in activation in lateral occipital cortex and fusiform gyrus, which are involved in visual processing of objects and faces, respectively. Furthermore, greater activation in these visual processing regions was associated with better subsequent memory for pairs over and above the effect of age and of hippocampal and pFC activation on performance. Recruitment of these visual processing regions mediated the association between age and memory performance, over and above the effects of hippocampal activation. Taken together, these findings extend the existing literature to suggest that greater recruitment of category-preferential visual processing regions during encoding of associative memories is a neural mechanism explaining improved memory across development.

scholarly journals No Evidence for Improved Associative Memory Performance Following Process-Based Associative Memory Training in Older Adults

2017 ◽  
Vol 8 ◽  
Author(s):  
Martin Bellander ◽  
Anne Eschen ◽  
Martin Lövdén ◽  
Mike Martin ◽  
Lars Bäckman ◽  
...  
Keyword(s):  
Older Adults ◽  
Associative Memory ◽  
Memory Performance ◽  
Memory Training

Cache memory performance in a unix enviroment

1986 ◽  
Vol 14 (3) ◽  
pp. 41-61 ◽  
Author(s):  
Cedell Alexander ◽  
William Keshlear ◽  
Furrokh Cooper ◽  
Faye Briggs
Keyword(s):  
Memory Performance ◽  
Cache Memory
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