Secure Hardware Design for Trust

Mapping Intimacies ◽

10.21236/ada597771 ◽

2014 ◽

Author(s):

Garrett S. Rose

Keyword(s):

Hardware Design ◽

Secure Hardware

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Secure Hardware Design for Trust

10.21236/ada566362 ◽

2012 ◽

Author(s):

Youngok Pino ◽

Garrett S. Rose

Keyword(s):

Hardware Design ◽

Secure Hardware

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Secure Hardware Design: Starting from the Roots of Trust

2021 IEEE European Test Symposium (ETS) ◽

10.1109/ets50041.2021.9465373 ◽

2021 ◽

Keyword(s):

Hardware Design ◽

Secure Hardware

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Course on secure hardware design of silicon chips

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2017.0028 ◽

2017 ◽

Vol 11 (4) ◽

pp. 304-309 ◽

Author(s):

Basel Halak

Keyword(s):

Hardware Design ◽

Silicon Chips ◽

Secure Hardware

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Register transfer level information flow tracking for provably secure hardware design

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 ◽

10.23919/date.2017.7927266 ◽

2017 ◽

Author(s):

Armaiti Ardeshiricham ◽

Wei Hu ◽

Joshua Marxen ◽

Ryan Kastner

Keyword(s):

Information Flow ◽

Hardware Design ◽

Register Transfer Level ◽

Information Flow Tracking ◽

Register Transfer ◽

Secure Hardware ◽

Level Information ◽

Provably Secure

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Building Blocks and Tools for Secure Hardware Design

2019 IEEE 8th International Workshop on Advances in Sensors and Interfaces (IWASI) ◽

10.1109/iwasi.2019.8791327 ◽

2019 ◽

Keyword(s):

Hardware Design ◽

Building Blocks ◽

Secure Hardware

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Secure hardware design through bit-tight information flow control

2013 IEEE International Conference of IEEE Region 10 (TENCON 2013) ◽

10.1109/tencon.2013.6718912 ◽

2013 ◽

Author(s):

Baolei Mao ◽

Wei Hu ◽

Yu Tai ◽

Huixiang Zhang ◽

Dejun Mu

Keyword(s):

Flow Control ◽

Information Flow ◽

Hardware Design ◽

Information Flow Control ◽

Secure Hardware

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Secure hardware design against side-channel attacks

10.31274/etd-180810-5414 ◽

2016 ◽

Author(s):

Jungmin Park

Keyword(s):

Hardware Design ◽

Side Channel ◽

Side Channel Attacks ◽

Secure Hardware

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A BDD based secure hardware design method to guard against power analysis attacks

18th International Symposium on VLSI Design and Test ◽

10.1109/isvdat.2014.6881088 ◽

2014 ◽

Author(s):

Partha De ◽

Kunal Banerjee ◽

Chittaranjan Mandal

Keyword(s):

Power Analysis ◽

Design Method ◽

Hardware Design ◽

Power Analysis Attacks ◽

Secure Hardware

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Constructive side-channel analysis for secure hardware design

2014 International Symposium on Integrated Circuits (ISIC) ◽

10.1109/isicir.2014.7029537 ◽

2014 ◽

Author(s):

Alexander Herrmann ◽

Marc Stottinger

Keyword(s):

Hardware Design ◽

Side Channel ◽

Side Channel Analysis ◽

Secure Hardware ◽

Channel Analysis

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VLSI Based Low Power Hardware Design Using Distributed Arithmetic (DA) Centered 2d Adam7 Transform For The Proposed Image Compression Algorithm

i-manager’s Journal on Embedded Systems ◽

10.26634/jes.2.2.2374 ◽

2013 ◽

Vol 2 (2) ◽

pp. 31-37

Author(s):

L. Vignesh ◽

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C. N. Marimuthu ◽

J. Joseph Lynn ◽

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...

Keyword(s):

Image Compression ◽

Low Power ◽

Hardware Design ◽

Compression Algorithm ◽

Distributed Arithmetic ◽

Image Compression Algorithm

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