scholarly journals STUDY OF AN ELECTRODELESS LAMP SYSTEM USING PHASE LOCKED LOOP CONTROL

1995 ◽  
Vol 79 (Appendix) ◽  
pp. 86-86
Author(s):  
Ichiro Yokozeki ◽  
Keiichi Shimizu ◽  
Mitsuhiro Matsuda ◽  
Kouzou Uemura ◽  
Akihiro Inouye
Keyword(s):  
Phase Locked Loop ◽  
Loop Control ◽  
Electrodeless Lamp ◽  
Lamp System

scholarly journals A study of protection circuit for 2.5MHz electrodeless lamp system

1997 ◽  
Vol 81 (Appendix) ◽  
pp. 77-77
Author(s):  
Hiroshi Kido ◽  
Yuji Kumagai ◽  
Shinji Makimura ◽  
Futoshi Okamoto
Keyword(s):  
Protection Circuit ◽  
Electrodeless Lamp ◽  
Lamp System

The FPGA-Based Phase-Locked Loop Speed Control System of BLDCM for Magnetically Suspended Control Moment Gyroscope

2011 ◽  
Vol 80-81 ◽  
pp. 1249-1257
Author(s):  
Bang Cheng Han ◽  
Dan He ◽  
Fang Zheng Guo ◽  
Yu Wang ◽  
Bing Nan Huang
Keyword(s):  
Control System ◽  
Integrated Circuit ◽  
High Speed ◽  
Speed Control ◽  
Phase Locked Loop ◽  
Buck Converter ◽  
Current Loop ◽  
Loop Control ◽  
Control Moment Gyroscope ◽  
Control Moment

A phase-locked loop (PLL) control system based on field programmable gates array (FPGA) is proposed through analyzing the model of three-phase unipolar-driven BLDCM (brushless direct current motor) to enhance the reliability and accurate steady-state speed for magnetically suspended control moment gyroscope (MSCMG). The numerical operation module, PLL module and current-loop control module are designed based on FPGA using very-high-speed integrated circuit hardware description language (VHDL) to realize the control law of the digital system. The pulse width modulation (PWM) generating module for Buck converter, the commutation signal generating module for the inverter and ADC module are designed for driving the motor and sampling the current signal. The PLL is analyzed and optimized in the paper and all the modules are verified using the software of ModelSim and the experiments. The simulation and experiment results on BLDCM of MSCMG show that the stability of the motor velocity can reach 0.01% and 0.02% respectively by the PLL technology based on FPGA, which is difficult to be obtained by conventional proportion integral different (PID) speed control.

Debugging Phase-Locked Loop Failures in Integrated Circuit Products

2014 ◽  
Author(s):  
S.H. Goh ◽  
Wendy Lau ◽  
B.L. Yeoh ◽  
H.W. Ho ◽  
G.F. You ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Frequency Control ◽  
Photon Emission ◽  
Building Blocks ◽  
Phase Locked Loop ◽  
Fault Isolation ◽  
Loop Control ◽  
Isolation Techniques ◽  
Loop Control System ◽  
Specific Frequency

Abstract A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.

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