Debugging Phase-Locked Loop Failures in Integrated Circuit Products

2014 ◽  
Author(s):  
S.H. Goh ◽  
Wendy Lau ◽  
B.L. Yeoh ◽  
H.W. Ho ◽  
G.F. You ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Frequency Control ◽  
Photon Emission ◽  
Building Blocks ◽  
Phase Locked Loop ◽  
Fault Isolation ◽  
Loop Control ◽  
Isolation Techniques ◽  
Loop Control System ◽  
Specific Frequency

Abstract A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.

The FPGA-Based Phase-Locked Loop Speed Control System of BLDCM for Magnetically Suspended Control Moment Gyroscope

2011 ◽  
Vol 80-81 ◽  
pp. 1249-1257
Author(s):  
Bang Cheng Han ◽  
Dan He ◽  
Fang Zheng Guo ◽  
Yu Wang ◽  
Bing Nan Huang
Keyword(s):  
Control System ◽  
Integrated Circuit ◽  
High Speed ◽  
Speed Control ◽  
Phase Locked Loop ◽  
Buck Converter ◽  
Current Loop ◽  
Loop Control ◽  
Control Moment Gyroscope ◽  
Control Moment

A phase-locked loop (PLL) control system based on field programmable gates array (FPGA) is proposed through analyzing the model of three-phase unipolar-driven BLDCM (brushless direct current motor) to enhance the reliability and accurate steady-state speed for magnetically suspended control moment gyroscope (MSCMG). The numerical operation module, PLL module and current-loop control module are designed based on FPGA using very-high-speed integrated circuit hardware description language (VHDL) to realize the control law of the digital system. The pulse width modulation (PWM) generating module for Buck converter, the commutation signal generating module for the inverter and ADC module are designed for driving the motor and sampling the current signal. The PLL is analyzed and optimized in the paper and all the modules are verified using the software of ModelSim and the experiments. The simulation and experiment results on BLDCM of MSCMG show that the stability of the motor velocity can reach 0.01% and 0.02% respectively by the PLL technology based on FPGA, which is difficult to be obtained by conventional proportion integral different (PID) speed control.

Debug and Fault Isolation of an RF/IF Circuit for 3G Cellular Applications With High Leakage: A Case Study

2002 ◽  
Author(s):  
Syd Wilson ◽  
Manoj Nair ◽  
Michael Vicker ◽  
Richard B. Meador ◽  
George Smoot ◽  
...  
Keyword(s):  
Leakage Current ◽  
Integrated Circuit ◽  
Photon Emission ◽  
Cost Effective ◽  
Fault Isolation ◽  
Cellular Phones ◽  
Third Generation ◽  
Mixed Signal ◽  
Emission Microscopy

Abstract First silicon of a cost effective, BICMOS mixed signal RF/IF integrated circuit (IC) for third generation (3G) cellular phones showed high leakage current on the analog receive supply pins in “battery save” mode. Our tasks were to identify and isolate the source of leakage and to fix the design. Alternate debug techniques were used to isolate the cause of the leakage and provide a solution after inconclusive results were obtained using photon emission microscopy,(1) and infrared microthermography techniques.

Design of Fault Diagnosis System for the Parameter-Depended Control System

2011 ◽  
Vol 320 ◽  
pp. 636-641
Author(s):  
Jing Zhou
Keyword(s):  
Control System ◽  
Fault Diagnosis ◽  
Fault Detection ◽  
Fault Isolation ◽  
Linear Matrix ◽  
Diagnosis System ◽  
Loop Control ◽  
Closed Loop Control System ◽  
Loop Control System ◽  
Fault Diagnosis System

A robust parameter-depended reduced order(RPRO) fault detection filter(FDF) is designed. Contrary to the parameter-depended uncertainty system, the order of the linear matrix inequalities is reduced, then the RPRO fault detection and fault isolated filters are constructed. Then a RPRO fault isolation filter is designed for occurrence of both actuator fault and sensor fault in the aerocraft’s closed-loop control system, and fault diagnosis system is structured based on the fault isolation filters. Through the output of the fault diagnosis system, we can alarm the fault timely and the advantages of this approach are highlighted.

Enhancing Point Defect Isolation by Using Ionizing Radiation

2019 ◽  
Author(s):  
Douglas J. Martin ◽  
Matthew J. Gadlage ◽  
Wai-Yat Leung ◽  
Jeffrey L. Titus
Keyword(s):  
Ionizing Radiation ◽  
Integrated Circuit ◽  
Focused Ion Beam ◽  
High Reliability ◽  
Ion Beam ◽  
Photon Emission ◽  
Fault Isolation ◽  
Oxide Semiconductor ◽  
Carrier Injection ◽  
Failure Site

Abstract An application-specific integrated circuit (ASIC) for a high reliability application is found to have a missing sidewall spacer in a single transistor. Manufacturer burn-in and standard component electrical tests do not capture this defect. The defect manifests after exposure to ionizing radiation. Photon emission microscopy (PEM), laser voltage imaging (LVI), and laserassisted device alteration (LADA) are used to isolate the failure site. At the failure site a focused ion beam (FIB) cross section indicates that a doubly doped drain (DDD) (N+) is likely present where a lightly doped drain (LDD) is designated. This defect leads to a failure mode that is consistent with hot-carrier injection in complementary metal-oxide semiconductor (CMOS) transistors. This paper presents the testability from a fault isolation aspect, shmoo plot characterization, and backside optical techniques to identify its spatial location. A discussion of the results includes why ionizing radiation allowed the defect’s capture and potential implications of using ionizing radiation as a viable failure analysis technique.

Backside Sample Preparation Challenges for Fault Localization Analysis of Flip Chip Package

2013 ◽  
Author(s):  
Lihong Cao ◽  
Donna Wallace ◽  
Lynda Tuttle ◽  
Kirk Martin
Keyword(s):  
Image Quality ◽  
Flip Chip ◽  
Thermal Emission ◽  
Photon Emission ◽  
Fault Isolation ◽  
Isolation Techniques ◽  
High Uniformity ◽  
Localization Analysis ◽  
Mechanical Thinning ◽  
The Impact

Abstract Mechanical thinning of Si die backside was introduced to support fault isolation for flip chip package in this paper. The backside milling system provides two types of thinning with good die planarity and mirror polishing to yield a high image quality for fault isolation techniques such as laser base thermal emission and photon emission techniques. In this paper, two mechanical thinning techniques were applied by using the 3D die curvature thinning and 2D planar thinning on flip chip Si backside. The impact of process parameters on die planarity and fault isolation were also discussed. The experimental results demonstrate the milling system’s high uniformity across the large die size and provide a very good solution for fault isolation techniques.

Combining Volume Scan Diagnosis and Dynamic Failure Analysis for Precise Isolation of Manufacturing Defects

2017 ◽  
Author(s):  
A.M. Jakati ◽  
R. Deshpande ◽  
K.A. Serrels ◽  
P. Babighian ◽  
G. Dabney ◽  
...  
Keyword(s):  
Semiconductor Manufacturing ◽  
Photon Emission ◽  
Fault Isolation ◽  
Manufacturing Defects ◽  
Voltage Imaging ◽  
Isolation Techniques ◽  
Advanced Technologies ◽  
Manufacturing Technologies ◽  
Non Destructive ◽  
Random Particle

Abstract Advances in semiconductor manufacturing technologies have led to newer types of defects that are difficult to identify, causing longer yield ramp times. Traditionally, yield has been limited to random particle defects but layout systematic defects are increasingly dominating the fail paretos on advanced technologies. Identifying systematic defects precisely and rapidly is a must. This paper codifies a methodology that combines volume scan diagnosis and non-destructive electrical fault isolation techniques such as photon-emission microscopy, soft defect localization and laser voltage imaging/probing to debug manufacturing defects precisely.

Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

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