Multipliers based on Approximate Compressors

2020 ◽  
Vol 12 ◽  
Author(s):  
Subhashis Maitra
Keyword(s):  
Image Processing ◽  
Comparative Study ◽  
Approximate Computing ◽  
Power Performance ◽  
Exact Computation

Background: Approximate computing is an emerging trend in recent year that trades off the requirement of exact computation for the improvement of speed and power performance. Objective: Researchers are trying to improve the speed and power performance proposing different algorithm. Method: This paper proposes approximate compressors used for the design of approximate multipliers. Results: By using the proposed method, approximate multipliers of different length have been synthesized and a comparative study with previously presented multipliers have been dealt here which shows that the proposed circuits have better speed and power. Conclusion: Finally the proposed circuits have been used for image processing applications.

scholarly journals Image Processing Architectures

2018 ◽  
pp. 68-74
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Image Quality ◽  
Comparative Study ◽  
Focal Plane ◽  
Detailed Review ◽  
Communication Problem ◽  
Fast Processing ◽  
Processing Architectures ◽  
The Comparative Study

One type of signal processing is Image processing in which the input used as an image and the output might also be an image or a set of features that are related to the image. Images are handled as a 2D signal using image processing methods. For the fast processing of images, several architectures are suitable for different responsibilities in the image processing practices are important. Various architectures have been used to resolve the high communication problem in image processing systems. In this paper, we will yield a detailed review about these image processing architectures that are commonly used for the purpose of getting higher image quality. Architectures discussed are FPGA, Focal plane SIMPil, SURE engine. At the end, we will also present the comparative study of MSIMD architecture that will facilitate to understand best one.

Power–Delay-Error-Efficient Approximate Adder for Error-Resilient Applications

2019 ◽  
Vol 28 (10) ◽  
pp. 1950171 ◽  
Author(s):  
Vinay Kumar ◽  
Ankit Singh ◽  
Shubham Upadhyay ◽  
Binod Kumar
Keyword(s):  
Image Processing ◽  
Power Consumption ◽  
Logic Gate ◽  
Logic Gates ◽  
Error Tolerance ◽  
Approximate Computing ◽  
Processing Application ◽  
Error Resilient ◽  
Delay Performance ◽  
Prime Concern

Power dissipation has been the prime concern for CMOS circuits. Approximate computing is a potential solution for addressing this concern as it reduces power consumption resulting in improved performance in terms of power–delay product (PDP). Decrease of power consumption in approximate computing is achieved by approximating the demand of accuracy as per the error tolerance of the system. This paper presents a new approach for designing approximate adder by introducing inexactness in the existing logic gate(s). Approximated logic gates provide flexibility in designing low power error-resilient systems depending on the error tolerance of the applications such as image processing and data mining. The proposed approximate adder (PAA) has higher accuracy than existing approximate adders with normalized mean error distance of 0.123 and 0.1256 for 16-bit and 32-bit adder, respectively, and lower PDP of 1.924E[Formula: see text]18[Formula: see text]J for 16-bit adder and 5.808E[Formula: see text]18[Formula: see text]J for 32-bit adder. The PAA also performs better than some of the recent approximate adders reported in literature in terms of layout area and delay. Performance of PAA has also been evaluated with an image processing application.

Comparative Study of Automatic Acquisition Methods of Image Processing Procedures.

2000 ◽  
pp. 311-314
Author(s):  
Toshihiro Hamada ◽  
Akinobu Shimizu ◽  
Toyofumi Saito ◽  
Jun-ichi Hasegawa ◽  
Jun-ichiro Toriwaki
Keyword(s):  
Image Processing ◽  
Comparative Study ◽  
Automatic Acquisition
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