scholarly journals Implementation of 6T-SRAM Cell using Conventional and Adiabatic Logic

2019 ◽  
Vol 7 (8) ◽  
pp. 71-80
Author(s):  
Irfan M. Trasgar
Keyword(s):  
Sram Cell ◽  
Adiabatic Logic

Design of SRAM Cell and Array Using Adiabatic Logic

2020 ◽  
pp. 1546-1552
Author(s):  
Mayilsamy M ◽  
Saravanakumar M ◽  
Rukkumani V ◽  
Sharmila B ◽  
Srinivasan K
Keyword(s):  
Sram Cell ◽  
Adiabatic Logic

scholarly journals Design of Low Power SRAM Cell Using Adiabatic Logic

2020 ◽  
Vol 1716 ◽  
pp. 012039
Author(s):  
Ramya sri Penugonda ◽  
V Ravi
Keyword(s):  
Low Power ◽  
Sram Cell ◽  
Adiabatic Logic

AN ENERGY-EFFICIENT ADIABATIC LOGIC BASED LFSR

2019 ◽  
Vol 7 (2) ◽  
pp. 1
Author(s):  
M. K. SAINI ◽  
N. PANDEY ◽  
NITISH ◽  
◽  
◽  
...  
Keyword(s):  
Energy Efficient ◽  
Adiabatic Logic

Evolutionary Approach of Adiabatic Logic Design on Low Power Solution �A Robust Survey

2012 ◽  
Vol 1 (2) ◽  
pp. 36-49
Author(s):  
A. Kishore Kumar ◽  
D. Somasundareswari ◽  
V. Duraisamy ◽  
T. Shunbaga Pradeepa
Keyword(s):  
Low Power ◽  
Evolutionary Approach ◽  
Logic Design ◽  
Adiabatic Logic

Ultralow-Power and Secure S-Box Circuit Using FinFET Based ECRL Adiabatic Logic

2018 ◽  
Vol 10 (3) ◽  
Author(s):  
K. Srilakshmi ◽  
◽  
A. V. N. Tilak ◽  
K. Srinivasa Rao ◽  
◽  
...  
Keyword(s):  
Adiabatic Logic ◽  
Ultralow Power

A New Approach for SRAM Soft Defect Root Cause Identification

2007 ◽  
Author(s):  
Peter Egger ◽  
Stefan Müller ◽  
Martin Stiftinger
Keyword(s):  
Integrated Circuits ◽  
Top Down ◽  
Feature Size ◽  
Design Rules ◽  
New Approach ◽  
Root Cause ◽  
Wafer Fab ◽  
Sram Cell ◽  
Tcad Simulation ◽  
Root Cause Identification

Abstract With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.

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