Vertical nanowire/nanosheet FETs with a horizontal channel for threshold voltage modulation

A new type of vertical nanowire (VNW)/nanosheet (VNS) FETs combining a horizontal channel (HC) with bulk/back-gate electrode configuration, including Bulk-HC and FD-SOI-HC VNWFET, is proposed and investigated by TCAD simulation. Comparisons were carried out between conventional VNWFET and the proposed devices. FD-SOI-HC VNWFET exhibits better I on/I off ratio and DIBL than Bulk-HC VNWFET. The impact of channel doping and geometric parameters on the electrical characteristic and body factor (γ) of the devices was investigated. Moreover, threshold voltage modulation by bulk/back-gate bias was implemented and a large γ is achieved for wide range V th modulation. In addition, results of I on enhancement and I off reduction indicate the proposed devices are promising candidates for performance and power optimization of NW/NS circuits by adopting dynamic threshold voltage management. The results of preliminary experimental data are discussed as well.

Optimization techniques for p-GTO thyristor design

A new type of semiconductor power device was devised in the early ’90s as an alternative to the classic Gate Turn-Off (GTO) thyristor. Because the low-doped n-base was replaced by a low-doped p-base, it was called the p-GTO. Its main advantage is a higher possible control voltage when the device is switched off, leading to the possibility of a higher blocking anode current (IATO) and a lower turn-off time. The studies and techniques employed with the help of SILVACO-TCAD simulation software Athena and Atlas show that the p-GTO has higher breakdown voltages compared with its classic counterpart and similar on-state voltage (VT) and switching characteristics when replacing the GTO in the same circuit. Specific circuit improvements, like an affordable higher turn-off gate voltage, will drive the p-GTO into even faster switching operation.

Prediction of Static Characteristic Parameters of an Insulated Gate Bipolar Transistor Using Artificial Neural Network

Breakdown voltage (BV), on-state voltage (Von), static latch-up voltage (Vlu), static latch-up current density (Jlu), and threshold voltage (Vth), etc., are critical static characteristic parameters of an IGBT for researchers. Von and Vth can characterize the conduction capability of the device, while BV, Vlu, and Jlu can help designers analyze the safe operating area (SOA) of the device and its reliability. In this paper, we propose a multi-layer artificial neural network (ANN) framework to predict these characteristic parameters. The proposed scheme can accurately fit the relationship between structural parameters and static characteristic parameters. Given the structural parameters of the device, characteristic parameters can be generated accurately and efficiently. Compared with technology computer-aided design (TCAD) simulation, the average errors of our scheme for each characteristic parameter are within 8%, especially for BV and Vth, while the errors are controlled within 1%, and the evaluation speed is improved more than 107 times. In addition, since the prediction process is mathematically a matrix operation process, there is no convergence problem, which there is in a TCAD simulation.

A 1.2 kV SiC MOSFET with Integrated Heterojunction Diode and P-shield Region

A 1.2 kV SiC MOSFET with an integrated heterojunction diode and p-shield region (IHP-MOSFET) was proposed and compared to a conventional SiC MOSFET (C-MOSFET) using numerical TCAD simulation. Due to the heterojunction diode (HJD) located at the mesa region, the reverse recovery time and reverse recovery charge of the IHP-MOSFET decreased by 62.5% and 85.7%, respectively. In addition, a high breakdown voltage (BV) and low maximum oxide electric field (EMOX) could be achieved in the IHP-MOSFET by introducing a p-shield region (PSR) that effectively disperses the electric field in the off-state. The proposed device also exhibited 3.9 times lower gate-to-drain capacitance (CGD) than the C-MOSFET due to the split-gate structure and grounded PSR. As a result, the IHP-MOSFET had electrically excellent static and dynamic characteristics, and the Baliga’s figure of merit (BFOM) and high frequency figure of merit (HFFOM) were increased by 37.1% and 72.3%, respectively. Finally, the switching energy loss was decreased by 59.5% compared to the C-MOSFET.

Analysis of Electrical Characteristics in 4H-SiC Trench-Gate MOSFETs with Grounded Bottom Protection p-Well Using Analytical Modeling

A new analytical model to analyze and optimize the electrical characteristics of 4H-SiC trench-gate metal-oxide-semiconductor field-effect transistors (TMOSFETs) with a grounded bottom protection p-well (BPW) was proposed. The optimal BPW doping concentration (NBPW) was extracted by analytical modeling and a numerical technology computer-aided design (TCAD) simulation, in order to analyze the breakdown mechanisms for SiC TMOSFETs using BPW, while considering the electric field distribution at the edge of the trench gate. Our results showed that the optimal NBPW obtained by analytical modeling was almost identical to the simulation results. In addition, the reverse transfer capacitance (Cgd) values obtained from the analytical model correspond with the results of the TCAD simulation by approximately 86%; therefore, this model can predict the switching characteristics of the effect BPW regions.

TCAD simulation for capture / emission of carriers by traps in SiN: trap-assisted tunneling model extended for capture of carriers injected via Fowler-Nordheim tunneling

We propose the novel trap-assisted tunneling (TAT) model that incorporates the ability to calculate dissipation of the kinetic energy of carriers propagating in the conduction or valence band. The proposed model allows us to evaluate capture efficiency (or the capture cross section) of carriers injected into the SiN charge trap layer via Fowler-Nordheim tunneling. By applying our TAT model to large planar Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) capacitors, experimental data showing that electron capture efficiency depends on the tunnel oxide thickness are physically interpreted. Furthermore, 3-dimensional technology computer-aided design (TCAD) simulation using SiN trap parameters roughly extracted from planar MONOS data shows that the calculated incremental step pulse programming characteristics of the charge trap memory (CTM) prototype device are comparable with measured data. We have found that additional time to calculate SiN trap charges is less than only 5 % of all remaining calculation time.

High-performance SiC MOSFET embedded heterojunction diode with electric field protection region

In this study, we proposed high-performance SiC MOSFET embedded heterojunction diode (HJD) with an electric field protection (EFP) region and analyzed it using a Sentaurus TCAD simulation. The proposed device features an HJD positioned at the trench side wall in the middle of the JFET region and a highly doped EFP region under the P+ polysilicon to features excellent static performance and high reliability. The simulation results revealed that the maximum oxide electric field (EMOX) and the Baliga’s figure-of-merit (BFOM) improved by 54% and 12%, respectively, compared with those of conventional SiC MOSFETs (C-MOSFETs). In addition, the EFP region suppressed the DIBL effect and leakage current in the HJD interface sufficiently. The HJD suppressed the bipolar degradation of the PiN body diode effectively due to its low VF (1.75 V). In addition, the proposed device demonstrated superior reverse-recovery characteristics, thereby improving trr and Qrr by 35% and 57%, respectively, compared to the corresponding values in C-MOSFET. Moreover, the input capacitance (CISS) was reduced by 17.5%, and CGD was reduced by 96%. Therefore, the high-frequency figure-of-merit (HFOM) improved by a factor of 25.8 in terms of RON × CGD. As a result, the proposed device is a promising structure for high-frequency and high-reliability applications.

Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers

In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.