scholarly journals A Clock and Data Recovery Circuit for the ALTAS/CMS HL-LHC Pixel Front End Chip in 65 nm CMOS Technology

2020 ◽  
Author(s):  
Konstantinos Moustakas ◽  
P. Rymaszewski ◽  
T. Hemperek ◽  
H. Krüger ◽  
M. Vogt ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Front End

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

2009 ◽  
Vol 56 (1) ◽  
pp. 6-10 ◽  
Author(s):  
Young-Suk Seo ◽  
Jang-Woo Lee ◽  
Hong-Jung Kim ◽  
Changsik Yoo ◽  
Jae-Jin Lee ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

scholarly journals A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems

Sensors ◽  
2018 ◽  
Vol 18 (8) ◽  
pp. 2709
Author(s):  
Sang-Hoon Kim ◽  
Hoon Shin ◽  
Youngkyun Jeong ◽  
June-Hee Lee ◽  
Jaehyuk Choi ◽  
...  
Keyword(s):  
Transition Density ◽  
Complementary Metal Oxide Semiconductor ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Image Sensor ◽  
Data Recovery ◽  
Oxide Semiconductor ◽  
Dual Channel ◽  
Charge Recycling ◽  
The Common

We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The direct current (DC)-coupled receiver front-end circuits manage the common-mode level variations and compensate for the channel loss. The tracked oversampling clock and data recovery (CDR), which realizes fast lock acquisition below 1 baud period and low logic latency, is shared by the two channels. Fabricated in a 65-nm low-power complementary metal-oxide semiconductor (CMOS) technology, the dual-channel transceiver achieves 12-Gb/s data rate while the transmitter consumes 20.43 mW from a 1.2-V power supply.

Sign in / Sign up

Export Citation Format

Share Document