Energy Efficiency in Slew-Rate Enhanced Single-Stage OTAs for Switched-Capacitor Applications

Slew-rate enhancement (SRE) techniques assist the charge transfer process in OTA-based switched-capacitor circuits. Parallel-type slew-rate enhancement circuits, i.e., circuits that provide a feed-forward path external to the main OTA, are attractive solutions, since they introduce a further degree of freedom in the speed/power consumption design space without affecting other specifications regarding the main OTA. This technique lends itself to be employed jointly with advanced OTA topologies in order to compose a highly energy efficient OTA/SRE system. However, insights in design choices such as power optimization are still missing for such systems. Here we discuss system level choices with the help of a simple model. Using precise electrical simulations, we demonstrate energy savings greater than 30% for different OTA/SRE systems implemented in a standard 180-nm CMOS technology.

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Passive slew rate enhancement technique for Switched-Capacitor Circuits

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2019.8885160 ◽

2019 ◽

Cited By ~ 1

Author(s):

Manjunath Kareppagoudr ◽

Emanuel Caceres ◽

Yu-Wen Kuo ◽

Jyotindra Shakya ◽

Yanchao Wang ◽

...

Keyword(s):

Switched Capacitor ◽

Slew Rate ◽

Rate Enhancement ◽

Enhancement Technique ◽

Switched Capacitor Circuits

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A single-stage operational amplifier with enhanced transconductance and slew rate for switched-capacitor circuits

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-014-0292-2 ◽

2014 ◽

Vol 79 (3) ◽

pp. 589-598 ◽

Cited By ~ 17

Author(s):

Mohammad Yavari ◽

Tohid Moosazadeh

Keyword(s):

Operational Amplifier ◽

Single Stage ◽

Switched Capacitor ◽

Slew Rate ◽

Switched Capacitor Circuits

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Performance Analysis and Design Optimization of Parallel-Type Slew-Rate Enhancers for Switched-Capacitor Applications

Electronics ◽

10.3390/electronics9111949 ◽

2020 ◽

Vol 9 (11) ◽

pp. 1949

Author(s):

Alessandro Catania ◽

Mattia Cicalini ◽

Michele Dei ◽

Massimo Piotto ◽

Paolo Bruschi

Keyword(s):

Power Efficiency ◽

Settling Time ◽

Current Gain ◽

Design Parameters ◽

Switched Capacitor ◽

Slew Rate ◽

Simple Modification ◽

Analysis And Design ◽

Time Reduction ◽

Parallel Type

The design of single-stage OTAs for accurate switched-capacitor circuits involves challenging trade-offs between speed and power consumption. The addition of a Slew-Rate Enhancer (SRE) circuit placed in parallel to the main OTA (parallel-type SRE) constitutes a viable solution to reduce the settling time, at the cost of low-power overhead and no modifications of the main OTA. In this work, a practical analytical model has been developed to predict the settling time reduction achievable with OTA/SRE systems and to show the effect of the various design parameters. The model has been applied to a real case, consisting of the combination of a standard folded-cascode OTA with an existing parallel-type SRE solution. Simulations performed on a circuit designed with a commercial 180-nm CMOS technology revealed that the actual settling-time reduction was significantly smaller than predicted by the model. This discrepancy was explained by taking into account the internal delays of the SRE, which is exacerbated when a high output current gain is combined with high power efficiency. To overcome this problem, we propose a simple modification of the original SRE circuit, consisting in the addition of a single capacitor which temporarily boosts the OTA/SRE currents reducing the internal turn-on delay. With the proposed approach a settling-time reduction of 57% has been demonstrated with an SRE that introduces only a 10% power-overhead with respect of the single OTA solution. The robustness of the results have been validated by means of Monte-Carlo simulations.

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