Making the PI and PID Controller Tuning Inspired by Ziegler and Nichols Precise and Reliable

This paper deals with the design of a DC motor speed control implemented by an embedded controller. The design is simple and brings some important changes to the traditional Ziegler–Nichols tuning. The design also includes a novel anti-windup implementation of the controller and an integrated noise-reduction filter design. The proposed tuning method considers all important aspects of the control, such as pre-processing of the measured signals and filtering (to attenuate the measurement noise), time delays of the process, modeling and identification of the process, and constraints on the control signal. Three important aspects of designing PI and PID controllers for processes with noisy output on Arduino-type embedded computers are considered. First, it deals with the integrated design of the input filter and the controller parameters, since both are interdependent. Secondly, the method of setting the controllers from step responses by Ziegler and Nichols is modified for the case of digital signal processing (without drawing the tangent), while it recommends the suitability of its modification in terms of the use of both integral and static models. Third, the most suitable anti-windup solution for the given controller structure is proposed. In summary, the paper shows that an appropriate design of the embedded controller can achieve excellent closed-loop performance even in a noisy process environment with limited control signals.

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Design and comparative study of PID controller tuning method from IMC tuned 2-DOF pole placement parameter structure for the DC motor speed control application

2013 Nirma University International Conference on Engineering (NUiCONE) ◽

10.1109/nuicone.2013.6780186 ◽

2013 ◽

Cited By ~ 1

Author(s):

Sandip Mehta ◽

Priyal Shah ◽

Vishal Vaidya

Keyword(s):

Comparative Study ◽

Pid Controller ◽

Speed Control ◽

Dc Motor ◽

Pole Placement ◽

Motor Speed ◽

Controller Tuning ◽

Tuning Method ◽

Pid Controller Tuning ◽

Control Application

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Tuning Methods of PID Controller for DC Motor Speed Control

Indonesian Journal of Electrical Engineering and Computer Science ◽

10.11591/ijeecs.v3.i2.pp343-349 ◽

2016 ◽

Vol 3 (2) ◽

pp. 343 ◽

Cited By ~ 9

Author(s):

Ashwaq Abdulameer ◽

Marizan Sulaiman ◽

MSM Aras ◽

Dawood Saleem

Keyword(s):

Pid Controller ◽

Engineering Students ◽

Speed Control ◽

Dc Motor ◽

Motor Speed ◽

Tuning Method ◽

Pid Tuning ◽

Pid Controller Tuning ◽

Long Time ◽

Tuning Methods

The traditional PID controllers are used for a long time to control the DC motor for many industrial processes, that because of the simplicity, flexibility, and satisfactory performance of this type of controller. This paper discusses the basic PID tuning method (Ziegler-Nichols) and its modification (Chien-Hrones-Reswick). Also, analysis the speed control DC motor response using the PID controller parameters that result from the tuning methods mentioned earlier. Moreover, explain the advantage and disadvantage of each formula of these methods. GUL/MATLAB windows used to implementing both methods to create more comfortable and friendly environment for better understanding of the PID controller tuning methods formula for engineering students and practicing engineers.

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DESIGN OF OPTIMAL PID CONTROLLER FOR THREE PHASE INDUCTION MOTOR BASED ON ANT COLONY OPTIMIZATION

SINERGI ◽

10.22441/sinergi.2020.2.006 ◽

2020 ◽

Vol 24 (2) ◽

pp. 125 ◽

Cited By ~ 1

Author(s):

Muhammad Ruswandi Djalal ◽

Faisal Faisal

Keyword(s):

Ant Colony Optimization ◽

Induction Motor ◽

Pid Controller ◽

Fitness Function ◽

Ant Colony ◽

Food Sources ◽

Optimal Parameters ◽

Motor Speed ◽

Tuning Method ◽

Pid Controller Tuning

Speed control of an induction motor is an important part of the operation of an induction motor. One method of regulating motor speed is the addition of a PID controller. PID parameters must be tuned properly to get the optimal speed. In this study, the PID controller tuning method uses an artificial intelligence method based on Ant Colony Optimization (ACO). ACO algorithm in an intelligent algorithm that is inspired by the behavior of ants looking for food sources in groups with traces of feromone left behind. In this study, food sources are represented as optimal parameters of PID. From the computational results obtained optimal parameters respectively, P (Proportional) 0.5359, I (Integral) 0.1173, D (Derivative) 0.0427. ACO computing found the optimal parameters in the 21st iteration with a minimum fitness function of 11.8914. Case studies are used with two variations of the speed of the induction motor input. With optimal tuning, the performance of the induction motor is increasing, marked by a minimum overshoot of 1.08 pu and a speed variation of both overshoots of 1,201 pu, whereas without control 1.49 pu and 1.28 pu, as well as with PID trial control of 1.22 pu and 1.23 pu respectively. The benefits of this research can be used as a reference for the operation of induction motors, by tuning the Ant Colony intelligent method for the PID controller in real-time with the addition of microcontroller components.

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High-Order Filtered PID Controller Tuning Based on Magnitude Optimum

Mathematics ◽

10.3390/math9121340 ◽

2021 ◽

Vol 9 (12) ◽

pp. 1340

Author(s):

Damir Vrančić ◽

Mikuláš Huba

Keyword(s):

A Priori ◽

Higher Order ◽

Process Models ◽

Pid Controllers ◽

Tuning Method ◽

Output Noise ◽

Pid Controller Tuning ◽

Output Time ◽

Tuning Methods ◽

Measured Input

The paper presents a tuning method for PID controllers with higher-order derivatives and higher-order controller filters (HO-PID), where the controller and filter orders can be arbitrarily chosen by the user. The controller and filter parameters are tuned according to the magnitude optimum criteria and the specified noise gain of the controller. The advantages of the proposed approach are twofold. First, all parameters can be obtained from the process transfer function or from the measured input and output time responses of the process as the steady-state changes. Second, the a priori defined controller noise gain limits the amount of HO-PID output noise. Therefore, the method can be successfully applied in practice. The work shows that the HO-PID controllers can significantly improve the control performance of various process models compared to the standard PID controllers. Of course, the increased efficiency is limited by the selected noise gain. The proposed tuning method is illustrated on several process models and compared with two other tuning methods for higher-order controllers.

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Time-Domain Matrix Analysis of Polyphase FIR Filters

International Journal of Electrical Engineering Education ◽

10.7227/ijeee.49.3.7 ◽

2012 ◽

Vol 49 (3) ◽

pp. 275-290

Author(s):

Eric J. Balster ◽

Francis D. Fradette ◽

Frank A. Scarpino ◽

Kerry L. Hill

Keyword(s):

Time Domain ◽

Filter Design ◽

Digital Signal ◽

Time Domain Analysis ◽

Discrete Systems ◽

Domain Analysis ◽

Matrix Analysis ◽

Student Survey ◽

Z Domain ◽

Polyphase Filters

Polyphase filter design is a common subject studied in discrete systems analysis and digital signal processing (DSP) courses. However, the classic z-domain analysis, utilizing the noble identities, gives a conclusion to the true physical structures of polyphase filters which may not be obvious to many students. The proposed time-domain analysis provides a more straightforward development of polyphase implementation of interpolation and decimation functions, and hopes to provide students with a more visual representation of the polyphase interpolation and decimation processes. Results from a student survey show that over 73% of students believe that the proposed polyphase analysis strengthened their understanding of polyphase filters, and over 71% would prefer to use the proposed method over the traditional z-domain analysis when explaining polyphase filters to others.

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A novel PID controller tuning method based on optimization technique

Journal of Central South University of Technology ◽

10.1007/s11771-010-0595-0 ◽

2010 ◽

Vol 17 (5) ◽

pp. 1036-1042 ◽

Cited By ~ 8

Author(s):

Xi-ming Liang ◽

Shan-chun Li ◽

A. B. Hassan

Keyword(s):

Pid Controller ◽

Optimization Technique ◽

Controller Tuning ◽

Tuning Method ◽

Pid Controller Tuning

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FPGA Implementation of Proficient 16-Tap FIR Filter Design Using Decision Tree Algorithm

Turkish Journal of Computer and Mathematics Education (TURCOMAT) ◽

10.17762/turcomat.v12i5.809 ◽

2021 ◽

Vol 12 (5) ◽

pp. 170-180

Author(s):

A Murali, K Hari Kishore

Keyword(s):

Signal Processing ◽

Filter Design ◽

Finite Impulse Response ◽

Digital Signal ◽

Channel Structure ◽

Decision Tree Algorithm ◽

Variable Size ◽

Structure Channel ◽

Fir Filter Design ◽

Dsp Applications

Lately, channel is one of the key components in signal handling applications. Among different channels, Finite Impulse Response (FIR) channel is broadly utilized in Digital Signal Processing (DSP) applications for shifting/denoising. For enormous scope coordination (VLSI) execution of fixed-coefficient FIR channels, huge asset used customary multipliers that can be acknowledged by a solitary steady multiplication (SCM) and numerous consistent augmentations (MCM) square utilizing movement and include/take away tasks. For a proficient execution, a variable size apportioning approach is proposed in direct structure channel structure that devours less zone and 11% of decrease in basic way delay, 40% decrease of all out force utilization, 15% decrease of zone delay product(ADP), 52% decrease of vitality delay product(EDP), and 42% decrease of intensity territory product(PAP), on a normal, over the cutting edge techniques. In this paper, a state choice tree calculation is proposed to decrease unpredictability in channel tap cells of variable size apportioning approach. The proposed plot creates a choice tree to perform move and expansion/deduction and aggregation dependent on the consolidated SCM/MCM approach. This plan diminishes the quantity of postpone registers required for tab cells. The proposed snake design will be actualized in Xilinx Zed, Spartan and Virtex devices and Area, power and speed investigation will be performed.

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