scholarly journals Design and Analysis of Closed Loop Control of Multilevel SVPWM Inverter Fed PMSM Drive

Permanent magnet synchronous machines have been universally used over induction machines in variable speed drives. For present trends and future developments, power electronics technology gives the extensive research of multilevel inverters that brings high safety voltages with low harmonic content in comparison with two-level inverter strategies. Multi level inverters implementation can be done by raising the number of power semi conductor controlled switching devices per phase to increase the number of inverter output voltage levels. By increasing the levels, power controlled switching devices and other components are increased, which makes the inverter complex and overpriced. From the above aspects, three-phase three-level inverter strategy is used for high performance and high voltage A.C drives. Multilevel inverter using a space vector pulse width modulation (SVPWM) strategy gives great advantages in high performance A.C drive applications. Various types of control strategies have been recommended for voltage source inverter fed A.C drives. In the proposed work, a PI controller is designed for the outer loop and non-linear controller using a state feedback linearization technique is designed for the inner loop. The closed loop control system for three-level inverter fed Permanent magnet synchronous motor drive employing SVPWM is extensively simulated using MATLAB.

2014 ◽  
Vol 654 ◽  
pp. 203-207
Author(s):  
Peng Fei Chen ◽  
Yue Nan Zeng ◽  
Zu Qun Peng ◽  
Li Zhi Wu

This article presents a program for permanent magnet synchronous motor (PMSM) vector control chip design based on SOPC technology. Microprocessor NIOSII and hardware arithmetic unit such as CORDIC and SVPWM, were all integrated in a FPGA by using bus interconnect and IP reuse technology, so that became a dedicated control chip of PMSM. Using hardware and software co-design methods, the chip was designed on Altera's CycloneIII FPGA, chip design flexibility and use small resource. Finally, combined with the power driver board achieved the dual closed-loop control of PMSM. The results show that system have a good performance, which proved that system can be well controlled by the designed IC.


Energies ◽  
2018 ◽  
Vol 11 (10) ◽  
pp. 2639 ◽  
Author(s):  
Joan Nicolas-Apruzzese ◽  
Emili Lupon ◽  
Sergio Busquets-Monge ◽  
Alfonso Conesa ◽  
Josep Bordonau ◽  
...  

This paper proposes a closed-loop control implementation fully-embedded into an FPGA for a permanent-magnet synchronous motor (PMSM) drive based on a four-level active-clamped converter. The proposed FPGA controller comprises a field-oriented control to drive the PMSM, a DC-link voltage balancing closed-loop control (VBC), and a virtual-vector-based modulator for a four-level active-clamped converter. The VBC and the modulator operate in consonance to preserve the DC-link capacitor voltages balanced. The FPGA design methodology is carefully described and the main aspects to achieve an optimal FPGA implementation using low resources are discussed. Experimental results under different operating conditions are presented to demonstrate the good performance and the feasibility of the proposed controller for motor-drive applications.


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