scholarly journals Issues on High Speed Relaying in High Voltage Transmission lines using Full Cycle Discrete Fourier Transform and Phaselet Transform

2019 ◽  
Vol 9 (2) ◽  
pp. 4953-4958
Keyword(s):  
Fourier Transform ◽  
Discrete Fourier Transform ◽  
High Voltage ◽  
Transmission Lines ◽  
High Speed ◽  
Response Times ◽  
Test System ◽  
Test Cases ◽  
Distance Relaying ◽  
Operational Issues

Now-a-days Phaselet Transform based distance relaying scheme is being proposed in the literature for high speed relaying in high voltage lines to obtain response times less than one quarter cycle. Phaselets are gaining importance due to their better transient response compared to Full Cycle Discrete Fourier Transform (FCDFT) during dynamic situations. But there are few operational issues with phaselets that have to be observed closely. In this paper, a single end feed test system with phaselet/FCDFT was simulated in MATLAB platform with various test cases. Then the performance of phaselet based distance relaying scheme is compared with the conventional Full Cycle Discrete Fourier Transform. Results are reported in this paper.

High Throughput Realization of a New Systolic Array based FFT using CORDIC

2012 ◽  
Vol 2 (2) ◽  
pp. 53-59
Author(s):  
Gourav Jain ◽  
Shaik Rafi Ahamed
Keyword(s):  
Fourier Transform ◽  
Discrete Fourier Transform ◽  
High Throughput ◽  
Systolic Array ◽  
Digital Computer ◽  
High Speed ◽  
Clock Cycle ◽  
Complex Multiplication ◽  
Computer Complex ◽  
Dsp Applications

In this paper, the authors propose a new systolic array for radix-2, N-point discrete Fourier Transform (DFT) computation based on CORDIC (CO-ordinate Rotation Digital Computer). Complex multiplication can be done by this in a rather simple and elegant way. A CORDIC based multiplier less DFT architecture is designed in order to improve the performance of the system. It is able to provide two transforms per each clock cycle. The proposed design is well suited for high speed DSP-applications.

On-line Adaptive and Intelligent Distance Relaying Scheme for Power Network

2015 ◽  
Vol 16 (5) ◽  
pp. 473-489
Author(s):  
Rahul Dubey ◽  
S. R. Samantaray ◽  
B. K. Panigrahi ◽  
G. V. Venkoparao
Keyword(s):  
Power Systems ◽  
Transmission Lines ◽  
Model Updating ◽  
Test System ◽  
Operating Conditions ◽  
Power Network ◽  
Parallel Transmission ◽  
On Line ◽  
Distance Relaying ◽  
Learning Machine

Abstract The paper presents an on-line sequential extreme learning machine (OS-ELM) based fast and accurate adaptive distance relaying scheme (ADRS) for transmission line protection. The proposed method develops an adaptive relay characteristics suitable to the changes in the physical conditions of the power systems. This can efficiently update the trained model on-line by partial training on the new data to reduce the model updating time whenever a new special case occurs. The effectiveness of the proposed method is validated on simulation platform for test system with two terminal parallel transmission lines with complex mutual coupling. The test results, considering wide variations in operating conditions of the faulted power network, indicate that the proposed adaptive relay setting provides significant improvement in the relay performance.

scholarly journals High-Speed Distance Relaying of the Entire Length of Transmission Lines Without Signaling

2020 ◽  
Vol 35 (4) ◽  
pp. 1949-1959
Author(s):  
Sadegh Azizi ◽  
Mingyu Sun ◽  
Gaoyuan Liu ◽  
Marjan Popov ◽  
Vladimir Terzija
Keyword(s):  
Transmission Lines ◽  
High Speed ◽  
Entire Length ◽  
Distance Relaying

scholarly journals Improving Generalized Discrete Fourier Transform (GDFT) Filter Banks with Low-Complexity and Reconfigurable Hybrid Algorithm

Digital ◽  
2020 ◽  
Vol 1 (1) ◽  
pp. 1-17
Author(s):  
Temidayo Otunniyi ◽  
Hermanus Myburgh
Keyword(s):  
Fourier Transform ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Discrete Fourier Transform ◽  
High Speed ◽  
Filter Bank ◽  
Filter Design ◽  
Low Complexity ◽  
Lookup Table ◽  
Research Attention

With ever-increasing wireless network demands, low-complexity reconfigurable filter design is expected to continue to require research attention. Extracting and reconfiguring channels of choice from multi-standard receivers using a generalized discrete Fourier transform filter bank (GDFT-FB) is computationally intensive. In this work, a lower compexity algorithm is written for this transform. The design employs two different approaches: hybridization of the generalized discrete Fourier transform filter bank with frequency response masking and coefficient decimation method 1; and the improvement and implementation of the hybrid generalized discrete Fourier transform using a parallel distributed arithmetic-based residual number system (PDA-RNS) filter. The design is evaluated using MATLAB 2020a. Synthesis of area, resource utilization, delay, and power consumption was done on a Quartus 11 Altera 90 using the very high-speed integrated circuits (VHSIC) hardware description language. During MATLAB simulations, the proposed HGDFT algorithm attained a 66% reduction, in terms of number of multipliers, compared with existing algorithms. From co-simulation on the Quartus 11 Altera 90, optimization of the filter with PDA-RNS resulted in a 77% reduction in the number of occupied lookup table (LUT) slices, an 83% reduction in power consumption, and an 11% reduction in execution time, when compared with existing methods.

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