METHOD FOR NONLINEARITY MINIMIZATION OF MULTIPLYING DIGITAL-TO-ANALOG CONVERTER BY LOW RESOLUTION CALIBRATION CONVERTER

2021 ◽  
pp. 87-93
Author(s):  
С.В. Калиниченко ◽  
Ю.С. Балашов ◽  
Д.Г. Харин ◽  
А.С. Шнайдер
Keyword(s):  
Nonvolatile Memory ◽  
Transfer Characteristic ◽  
Least Significant Bit ◽  
Low Resolution ◽  
Calculation Algorithm ◽  
Digital To Analog Converter ◽  
Differential Nonlinearity ◽  
Analog Converter ◽  
Field Programmable ◽  
Digital To Analog

Представлен метод минимизации нелинейности передаточной характеристики прецизионного умножающего цифро-аналогового преобразователя (ЦАП) с помощью вспомогательного корректирующего ЦАП малой разрядности. В данном методе вспомогательный ЦАП формирует искаженную передаточную характеристику, которая в сумме с передаточной характеристикой основного ЦАП позволяет уменьшить результирующую интегральную и дифференциальную нелинейность. Коэффициенты коррекции, рассчитанные согласно представленному в статье алгоритму, однократно записываются в энергонезависимую память и преобразуются в управляющий сигнал для калибрующего ЦАП с помощью арифметико-логического устройства (АЛУ) в зависимости от входных данных. Для проведения экспериментальных исследований был разработан макет системы калибровки на основе программируемой логической интегральной схемы (ПЛИС) и демонстрационной платы с микросхемой двухканального 16-разрядного ЦАП с сегментированной структурой. Представлены экспериментальные результаты, которые показывают, что в данной системе коррекции собственная нелинейность калибрующего ЦАП не оказывает существенного влияния на итоговую передаточную характеристику. Приведенный алгоритм расчета коэффициентов позволяет эффективно уменьшить абсолютную интегральную и дифференциальную нелинейность 16-разрядного ЦАП до значений менее 1 единицы веса младшего разряда (ЕМР) In this paper, we present a method for nonlinearity minimization of precision multiplying digital-to-analog converter (DAC) by utilizing low resolution calibration DAC. In this method the calibration DAC generates distorted transfer characteristic which is added to the main DAC characteristic and provides resulting integral and differential nonlinearity reduction. The calibration coefficients are calculated following the presented algorithm and saved in nonvolatile memory and then are converted to controlling digital code of calibration DAC by arithmetical-logical unit (ALU) depending on input data. For experimental research we designed a model of calibration system based on field programmable gate array (FPGA) and a demo board with dual 16-bit segmented DAC. Then we give experimental results which show that inherent nonlinearity of calibration DAC does not significantly affect overall nonlinearity. The proposed calculation algorithm obtains effective integral and differential nonlinearity minimization of 16-bit DAC down to values of less than one least significant bit (LSB)

scholarly journals A New Digital to Analog Converter Based on Low-Offset Bandgap Reference

2017 ◽  
Vol 2017 ◽  
pp. 1-10
Author(s):  
Jinpeng Qiu ◽  
Tong Liu ◽  
Xubin Chen ◽  
Yongheng Shang ◽  
Jiongjiong Mo ◽  
...  
Keyword(s):  
Operational Amplifier ◽  
Supply Voltage ◽  
Bandgap Reference ◽  
Digital To Analog Converter ◽  
Future Design ◽  
Differential Nonlinearity ◽  
Self Bias ◽  
Analog Converter ◽  
Digital To Analog ◽  
Low Offset

This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5 μm 5 V 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.

Increasing the information capacity of a fiber-optic multi-sensor converter of binary mechanical signals into electrical signals

2020 ◽  
pp. 15-23
Author(s):  
V. M. Grechishnikov ◽  
E. G. Komarov
Keyword(s):  
Fiber Optic ◽  
Information Capacity ◽  
Parallel Structure ◽  
Optical Scheme ◽  
Digital To Analog Converter ◽  
Electrical Signals ◽  
Mechanical Signals ◽  
Analog Converter ◽  
Output Code ◽  
Digital To Analog

The design and operation principle of a multi-sensor Converter of binary mechanical signals into electrical signals based on a partitioned fiber-optic digital-to-analog Converter with a parallel structure is considered. The digital-to-analog Converter is made from a set of simple and technological (three to five digit) fiber-optic digital-to-analog sections. The advantages of the optical scheme of the proposed. Converter in terms of metrological and energy characteristics in comparison with single multi-bit converters are justified. It is shown that by increasing the number of digital-analog sections, it is possible to repeatedly increase the information capacity of a multi-sensor Converter without tightening the requirements for its manufacturing technology and element base. A mathematical model of the proposed Converter is developed that reflects the features of its operation in the mode of sequential time conversion of the input code vectors of individual fiber-optic sections into electrical analogues and the formation of the resulting output code vector.

scholarly journals Coded Control of a Sectional Electroelastic Engine for Nanomechatronics Systems

2021 ◽  
Vol 4 (3) ◽  
pp. 47
Author(s):  
Sergey M. Afonin
Keyword(s):  
Transfer Function ◽  
Mechanical Load ◽  
Inertial Load ◽  
Digital To Analog Converter ◽  
Transient Characteristics ◽  
Analog Converter ◽  
Digital To Analog

This work determines the coded control of a sectional electroelastic engine at the elastic–inertial load for nanomechatronics systems. The expressions of the mechanical and adjustment characteristics of a sectional electroelastic engine are obtained using the equations of the electroelasticity and the mechanical load. A sectional electroelastic engine is applied for coded control of nanodisplacement as a digital-to-analog converter. The transfer function and the transient characteristics of a sectional electroelastic engine at elastic–inertial load are received for nanomechatronics systems.

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