scholarly journals Efficient FPGA Implementation of Modular Multiplication and Exponentiation

2020 ◽  
Vol 3 (1) ◽  
pp. 1-13
Author(s):  
M Issad ◽  
M Anane ◽  
B Boudraa ◽  
A M Bellemou ◽  
N Anane
Keyword(s):  
Execution Time ◽  
Public Key Cryptography ◽  
Fpga Implementation ◽  
Public Key ◽  
Modular Exponentiation ◽  
Modular Multiplication ◽  
Montgomery Modular Multiplication ◽  
Implementation Approach ◽  
On Chip ◽  
Data Length

This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated in Hardware (HW) as Programmable System on Chip (PSoC). The processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between execution time, occupied area and flexibility. In order to satisfy this constraint, Montgomery Power Ladder and Montgomery Modular Multiplication (MMM) algorithms are utilized for the ME and for the MM implementations as HW accelerators, respectively. Our implementation approach is based on the digit-serial method for performing the basic arithmetic operations. Efficient parallel and pipeline strategies are developed at the digit level for the optimization of the execution time. The application for 1024-bits data length shows that the MMM run in 6.24 µs and requires 647 slices. The ME is executed in 6.75 ms, using 2881 slices.

Efficient PSoC Implementation of Modular Multiplication and Exponentiation Based on Serial-Parallel Combination

2019 ◽  
Vol 28 (13) ◽  
pp. 1950229 ◽  
Author(s):  
M. Issad ◽  
B. Boudraa ◽  
M. Anane ◽  
A. M. Bellemou
Keyword(s):  
Input Data ◽  
Public Key Cryptography ◽  
Modular Exponentiation ◽  
Modular Multiplication ◽  
Montgomery Modular Multiplication ◽  
Implementation Approach ◽  
Security Levels ◽  
Data Bus ◽  
On Chip ◽  
Data Length

This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated as Programmable System on Chip (PSoC) where the processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between time execution, occupied area and flexibility. The implementation of these operations on such environment requires taking into account several criteria. Indeed, the Hardware (HW) architectures data bus should be smaller than the input data length. The design must be scalable to support different security levels. The implementation achieves optimums execution time and HW resources number. In order to satisfy these constraints, Montgomery Power Ladder (MPL) and Montgomery Modular Multiplication (MMM) algorithms are utilized for the ME and the MM implementations as HW accelerators, respectively. Our implementation approach is based on the digit-serial method for performing the basic arithmetic operations. Efficient parallel and pipeline strategies are developed at the digit level for the optimization of the execution times. The application for 1024-bits data length shows that the MMM run in 6.24[Formula: see text][Formula: see text]s and requires 647 slices. The ME is executed in 6.75[Formula: see text]ms using 2881 slices.

HIGH PERFORMANCE MONTGOMERY MODULAR MULTIPLIER WITH A NEW RECODING METHOD

2011 ◽  
Vol 20 (03) ◽  
pp. 531-548 ◽  
Author(s):  
KOOROUSH MANOCHEHRI ◽  
BABAK SADEGHIYAN ◽  
SAADAT POURMOZAFARI
Keyword(s):  
High Performance ◽  
Hardware Implementation ◽  
Computer Arithmetic ◽  
Public Key Cryptography ◽  
Modular Exponentiation ◽  
Modular Multiplication ◽  
Area Reduction ◽  
Montgomery Modular Multiplication ◽  
Modular Multiplier ◽  
Reduction In Area

Modular calculations are widely used in many applications, especially in public key cryptography. Such operations are very time consuming, due to their long operands. To improve the performance of these calculations, many methods have been introduced. Montgomery modular multiplication is an example of such a solution to enhance the performance of modular multiplication and modular exponentiation. The radix-2 version of this method is simple and fast for hardware implementation, where multi-operand adders are required for its implementation. So far, Carry-Save-Adder (CSA) gives the best performance for multi-addition. In this paper, we propose a new recoding method for the Montgomery modular multiplier to enhance its performance. This is done through replacing CSA blocks with new blocks that have better performances than CSA in multi-addition calculations. With this replacement, we can theoretically have up to 40% reduction in area gates. In our experiments, we obtained 5.8% area reduction and 3% speed improvement in a hardware implementation. The idea behind our proposed method is the use of bitwise subtraction operator, where no carry propagation is needed. This recoding method of operands can also be used in many aspects of computer arithmetic, algorithms and computational hardware, such as multiplication, exponentiation and etc., in order to enhance their performances.

An Improved Montgomery Window Algorithm on Modular Exponentiation Secure against Side Channel Attacks

2013 ◽  
Vol 392 ◽  
pp. 862-866
Author(s):  
Mu Han ◽  
Jia Zhao ◽  
Shi Dian Ma
Keyword(s):  
Public Key Cryptography ◽  
Public Key ◽  
Side Channel ◽  
Modular Exponentiation ◽  
Side Channel Attacks ◽  
The Core

As one of the core algorithms in most public key cryptography, modular exponentiation has a flaw of its efficiency, which often uses the Montgomerys algorithm to realize the fast operation. But the Montgomerys algorithm has the issue of side channel leakage from the final conditional subtraction. Aiming at this problem, this paper presents an improved fast Montgomery window algorithm. The new algorithm generates the remainder table with odd power to reduce the amount of pre-computation, and combines with the improved Montgomerys algorithm to realize modular exponentiation, which can accelerate the speed and reduce the side channel leakage. The new algorithm cant only thwart side channel attacks, but also improve the efficiency.

scholarly journals Revisiting Sum of Residues Modular Multiplication

2010 ◽  
Vol 2010 ◽  
pp. 1-9 ◽  
Author(s):  
Yinan Kong ◽  
Braden Phillips
Keyword(s):  
Public Key Cryptography ◽  
Number System ◽  
Residue Number System ◽  
The Other ◽  
Public Key ◽  
Modular Multiplication ◽  
Residue Number ◽  
The Cost

In the 1980s, when the introduction of public key cryptography spurred interest in modular multiplication, many implementations performed modular multiplication using a sum of residues. As the field matured, sum of residues modular multiplication lost favor to the extent that all recent surveys have either overlooked it or incorporated it within a larger class of reduction algorithms. In this paper, we present a new taxonomy of modular multiplication algorithms. We include sum of residues as one of four classes and argue why it should be considered different to the other, now more common, algorithms. We then apply techniques developed for other algorithms to reinvigorate sum of residues modular multiplication. We compare FPGA implementations of modular multiplication up to 24 bits wide. The sum of residues multipliers demonstrate reduced latency at nearly 50% compared to Montgomery architectures at the cost of nearly doubled circuit area. The new multipliers are useful for systems based on the Residue Number System (RNS).

A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs

2017 ◽  
Vol 1 (3) ◽  
pp. 219-236 ◽  
Author(s):  
Amine Mrabet ◽  
Nadia El-Mrabet ◽  
Ronan Lashermes ◽  
Jean-Baptiste Rigaud ◽  
Belgacem Bouallegue ◽  
...  
Keyword(s):  
Public Key ◽  
Modular Multiplication ◽  
Public Key Cryptosystems ◽  
Montgomery Modular Multiplication
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