Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching

2012 ◽  
pp. 198-218 ◽  
Author(s):  
Zheng Shi ◽  
Alan Burns ◽  
Leandro Soares Indrusiak
Keyword(s):  
Real Time ◽  
Schedulability Analysis ◽  
Analysis Approach ◽  
Worst Case ◽  
Real Time Analysis ◽  
Wormhole Switching ◽  
Latency Analysis ◽  
Network Latency ◽  
Simulation Results ◽  
On Chip

In this paper, the authors discuss a real-time on-chip communication service with a priority-based wormhole switching policy. The authors present a novel off-line schedulability analysis approach, worst case network latency analysis. By evaluating diverse inter-relationships and service attributes among the traffic flows, this approach can predict the packet network latency for all practical situations. The simulation results provide evidence that communication latency calculated using the real time analysis approach is safe, closely matching the figures obtained from simulation.

Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching

2010 ◽  
Vol 1 (2) ◽  
pp. 1-22 ◽  
Author(s):  
Zheng Shi ◽  
Alan Burns ◽  
Leandro Soares Indrusiak
Keyword(s):  
Real Time ◽  
Schedulability Analysis ◽  
Analysis Approach ◽  
Traffic Flows ◽  
Time Analysis ◽  
Worst Case ◽  
Real Time Analysis ◽  
Wormhole Switching ◽  
Network Latency ◽  
On Chip

In this paper, the authors discuss a real-time on-chip communication service with a priority-based wormhole switching policy. The authors present a novel off-line schedulability analysis approach, worst case network latency analysis. By evaluating diverse inter-relationships and service attributes among the traffic flows, this approach can predict the packet network latency for all practical situations. The simulation results provide evidence that communication latency calculated using the real time analysis approach is safe, closely matching the figures obtained from simulation.

Evaluation of a Connectionless Technique for System-on-Chip Interconnection

2016 ◽  
Vol 25 (10) ◽  
pp. 1630005 ◽  
Author(s):  
Marcelo Daniel Berejuck ◽  
Antônio A. Fröhlich
Keyword(s):  
Real Time ◽  
High Performance ◽  
Communication Channel ◽  
Resource Reservation ◽  
Multimedia Applications ◽  
Worst Case ◽  
Average Latency ◽  
On Chip ◽  
Hard Real Time

We present the design and evaluation of a high-performance network-on-chip (NoC) focused on telecommunication and multimedia applications that tolerate latency and bandwidth variations. The design is based on a connectionless strategy in which flits from different communication flows are interleaved in the same communication channel. Each flit carries routing information that is used by routers to perform arbitration and scheduling of the corresponding output ports in order to balance channel utilization. In order to compare our approach with others, we introduce an analytic model for the worst-case latency (WCL) of our NoC and recall those of related approaches. Analytic comparisons and experimental data show that our approach keeps average WCL lower for variable-bit-rate multimedia applications than a network based on resource reservation. For these applications, the overall throughput is larger than that of networks that perform resource reservation. A case study based on the proposed NoC shows that the average latency was 28% lower than the WCL expected for the experiment. Indeed, hard real-time flows designed considering the absolute WCL of the network will always meet the requirements of the associated hard real-time tasks, so no deadline can be lost due to network contention.

A real-time analysis approach in opportunistic networks

2011 ◽  
Vol 8 (3) ◽  
pp. 40-43 ◽  
Author(s):  
Rodrigo Santos ◽  
Javier Orozco ◽  
Sergio F. Ochoa
Keyword(s):  
Real Time ◽  
Opportunistic Networks ◽  
Analysis Approach ◽  
Time Analysis ◽  
Real Time Analysis

ACO-Based Global Optimal Transportation Path

2012 ◽  
Vol 488-489 ◽  
pp. 1680-1683
Author(s):  
Wei Hua Zhu ◽  
Ying Shen
Keyword(s):  
Ant Colony Optimization ◽  
Real Time ◽  
Shortest Path ◽  
Real Life ◽  
Optimal Transportation ◽  
Time Analysis ◽  
The Real ◽  
Real Time Analysis ◽  
Global Optimal ◽  
Simulation Results

This paper discusses how to address some issues when contemplating the global optimal transportation path (GOTP) such as dynamics, the ability of real-time analysis as well as complexity of prediction. Using shortest path methodology, this paper abstracts the real-life problem to a graphic context. Based on the solution of ant colony optimization (ACO) algorithm, the simulation indicates that this manner is efficient and effective in dealing with these problems. The indicators utilized ACO are achieved through simulation results analysis, providing the range of exact elements.

scholarly journals Task mapping and routing optimization for hard real-time Networks-on-Chip

2019 ◽  
Vol 8 (2) ◽  
pp. 414-421 ◽  
Author(s):  
M. Norazizi Sham Mohd Sayuti ◽  
Farida Hazwani Mohd Ridzuan ◽  
Zul Hilmi Abdullah
Keyword(s):  
Real Time ◽  
Optimization Technique ◽  
Network Routing ◽  
Design Parameters ◽  
Task Mapping ◽  
Evaluation Function ◽  
Worst Case ◽  
Networks On Chip ◽  
On Chip ◽  
Hard Real Time

Interference from high priority tasks and messages in a hard real-time Networks-on-Chip (NoC) create computation and communication delays. As the delays increase in number, maintaining the system’s schedulability become difficult. In order to overcome the problem, one way is to reduce interference in the NoC by changing task mapping and network routing. Some population-based heuristics evaluate the worst-case response times of tasks and messages based on the schedulability analysis, but requires a significant amount of optimization time to complete due to the complexity of the evaluation function. In this paper, we propose an optimization technique that explore both parameters simultaneously with the aim to meet the schedulability of the system, hence reducing the optimization time. One of the advantages from our approach is the unrepeated call to the evaluation function, which is unaddressed in the heuristics that configure design parameters in stages. The results show that a schedulable configuration can be found from the large design space.

Pendekatan Permodelan Masa Untuk Analisis Penjadualan Dalam Pembangunan Perisian Berasaskan Komponen

2012 ◽  
Author(s):  
Dayang Norhayati Abang Jawawi ◽  
Radziah Mohamad ◽  
Rosbi Mamat ◽  
Safaai Deris ◽  
Mohd Zulkifli Mohd Zaki
Keyword(s):  
Real Time ◽  
Scheduling Algorithm ◽  
Schedulability Analysis ◽  
Worst Case ◽  
Real Time System ◽  
Temporal Modeling ◽  
Temporal Models ◽  
Real Performance ◽  
Time Requirements ◽  
Time Systems

Dalam mereka bentuk sesebuah perisian masa–nyata terbenam, perkara penting yang perlu dititikberatkan ialah mengambil kira keperluan masa–nyata perisian tersebut. Kebolehan meramal dan menganalisis masa boleh menjamin keutuhan sesebuah sistem masa–nyata terbenam. Keperluan pemasaan bagi sistem masa–nyata terbenam mestilah dimodelkan dengan jelas semasa fasa keperluan dan fasa reka bentuk. Ini bertujuan untuk mengelakkan ralat permasaan berlaku semasa berada di lapangan dan menyebabkan kos yang banyak bagi kerja–semula pada peringkat akhir pembangunan. Analisis penjadualan merupakan alatan asas untuk menyemak ketepatan masa bagi sesebuah aplikasi masa–nyata. Kaedah analisis ini membolehkan proses menyemak faktor kekangan masa dengan meramal kes perlakuan terburuk bagi sesebuah sistem masa–nyata semasa algoritma penjadualan diaplikasikan. Kertas kerja ini mencadangkan satu pendekatan permodelan pemasaan di dalam pembangunan perisian yang berasaskan komponen dan menunjukkan bagaimana ramalan prestasi masa–nyata boleh dibuat berdasarkan model pemasaan tersebut. Satu eksperimen yang melibatkan kajian kes sistem masa–nyata terbenam telah direka bentuk untuk menunjukkan pendekatan yang dicadangkan ini dan juga mengesahkan keputusan ramalan prestasi sebenar perisian masa–nyata terbenam tersebut. Kata kunci: Sistem masa–nyata terbenam; analisis penjadualan; perisian berasaskan komponen An important issue in designing embedded real–time (ERT) software is the consideration for real–time requirements of the software. The abilities to predict and analyze timing are key requirements for reliable ERT systems. The temporal requirements of the ERT system must be explicitly modeled during requirements and design phases to avoid timing error in the field and costly late rework. Scheduling analysis is a fundamental tool for checking timing correctness of a real–time application. It allows checking timing constraints by predicting the worst–case behavior of a real–time system when a scheduling algorithm is applied. The aims of this paper are to propose an approach which enables temporal modeling and to demonstrate prediction of real–time performance based on the temporal models in component–based software development. An experiment on case–study was designed, to demonstrate the approach and to validate the predicted results against the real performance of an ERT software. Key words: Embedded real–time systems; schedulability analysis; component–based software

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