Implementation of Biologically Inspired Components in Embedded Vision Systems

2012 ◽  
pp. 307-345 ◽  
Author(s):  
Christopher Wing Hong Ngau ◽  
Li-Minn Ang ◽  
Kah Phooi Seng
Keyword(s):  
Field Programmable Gate Array ◽  
Resource Constraints ◽  
Low Complexity ◽  
Primary Concern ◽  
Complex Data ◽  
Biologically Inspired ◽  
Computational Speed ◽  
Visual Tasks ◽  
Field Programmable ◽  
Memory Resources

Studies in the area of computational vision have shown the capability of visual attention (VA) processing in aiding various visual tasks by providing a means for simplifying complex data handling and supporting action decisions using readily available low-level features. Due to the inclusion of computational biological vision components to mimic the mechanism of the human visual system, VA processing is computationally complex with heavy memory requirements and is often found implemented in workstations with unapplied resource constraints. In embedded systems, the computational capacity and memory resources are of a primary concern. To allow VA processing in such systems, the chapter presents a low complexity, low memory VA model based on an established mainstream VA model that addresses critical factors in terms of algorithm complexity, memory requirements, computational speed, and salience prediction performance to ensure the reliability of the VA processing in an environment with limited resources. Lastly, a custom softcore microprocessor-based hardware implementation on a Field-Programmable Gate Array (FPGA) is used to verify the implementation feasibility of the presented low complexity, low memory VA model.

Biologically Inspired Components in Embedded Vision Systems

2018 ◽  
pp. 458-493
Author(s):  
Li-Minn Ang ◽  
Kah Phooi Seng ◽  
Christopher Wing Hong Ngau
Keyword(s):  
Vision System ◽  
Low Complexity ◽  
Human Vision ◽  
Primary Concern ◽  
Resource Constrained ◽  
Vision Systems ◽  
Biologically Inspired ◽  
Embedded Vision ◽  
Field Programmable ◽  
Embedded Vision Systems

Biological vision components like visual attention (VA) algorithms aim to mimic the mechanism of the human vision system. Often VA algorithms are complex and require high computational and memory requirements to be realized. In biologically-inspired vision and embedded systems, the computational capacity and memory resources are of a primary concern. This paper presents a discussion for implementing VA algorithms in embedded vision systems in a resource constrained environment. The authors survey various types of VA algorithms and identify potential techniques which can be implemented in embedded vision systems. Then, they propose a low complexity and low memory VA model based on a well-established mainstream VA model. The proposed model addresses critical factors in terms of algorithm complexity, memory requirements, computational speed, and salience prediction performance to ensure the reliability of the VA in a resource constrained environment. Finally a custom softcore microprocessor-based hardware implementation on a Field-Programmable Gate Array (FPGA) is used to verify the implementation feasibility of the presented model.

Biologically Inspired Components in Embedded Vision Systems

2015 ◽  
Vol 3 (1) ◽  
pp. 39-72
Author(s):  
Li-Minn Ang ◽  
Kah Phooi Seng ◽  
Christopher Wing Hong Ngau
Keyword(s):  
Vision System ◽  
Low Complexity ◽  
Human Vision ◽  
Primary Concern ◽  
Resource Constrained ◽  
Vision Systems ◽  
Biologically Inspired ◽  
Embedded Vision ◽  
Field Programmable ◽  
Embedded Vision Systems

Biological vision components like visual attention (VA) algorithms aim to mimic the mechanism of the human vision system. Often VA algorithms are complex and require high computational and memory requirements to be realized. In biologically-inspired vision and embedded systems, the computational capacity and memory resources are of a primary concern. This paper presents a discussion for implementing VA algorithms in embedded vision systems in a resource constrained environment. The authors survey various types of VA algorithms and identify potential techniques which can be implemented in embedded vision systems. Then, they propose a low complexity and low memory VA model based on a well-established mainstream VA model. The proposed model addresses critical factors in terms of algorithm complexity, memory requirements, computational speed, and salience prediction performance to ensure the reliability of the VA in a resource constrained environment. Finally a custom softcore microprocessor-based hardware implementation on a Field-Programmable Gate Array (FPGA) is used to verify the implementation feasibility of the presented model.

scholarly journals A Hardware Accelerator for the Inference of a Convolutional Neural network

2019 ◽  
Vol 30 (1) ◽  
pp. 107-116 ◽  
Author(s):  
Edwin González ◽  
Walter D. Villamizar Luna ◽  
Carlos Augusto Fajardo Ariza
Keyword(s):  
Field Programmable Gate Array ◽  
System On Chip ◽  
Software Implementation ◽  
Hardware Accelerator ◽  
Processing Scheme ◽  
Field Programmable ◽  
Computationally Intensive ◽  
On Chip ◽  
Memory Resources ◽  
Better Than

Convolutional Neural Networks (CNNs) are becoming increasingly popular in deep learning applications, e.g. image classification, speech recognition, medicine, to name a few. However, the CNN inference is computationally intensive and demanding a large among of memory resources. In this work is proposed a CNN inference hardware accelerator, which was implemented in a co-processing scheme. The aim is to reduce the hardware resources and achieve the better possible throughput. The design was implemented in the Digilent Arty Z7-20 development board, which is based on System on Chip (SoC) Zynq-7000 of Xilinx. Our implementation achieved a  of accuracy for the MNIST database using only 12-bits fixed-point format. The results show that the co-processing scheme operating at a conservative speed of 100 MHz can identify around 441 images per second, which is about 17% times faster than a 650 MHz - software implementation. It is difficult to compare our results against other implementations based on Field-Programmable Gate Array (FPGA), because the others implementations are not exactly like ours. However, some comparisons, regarding the logical resources used and accuracy, suggest that our work could be better than previous works.

scholarly journals Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code

Electronics ◽  
2018 ◽  
Vol 8 (1) ◽  
pp. 10 ◽  
Author(s):  
Vicente Torres ◽  
Javier Valls ◽  
Maria Canet ◽  
Francisco García-Herrero
Keyword(s):  
Field Programmable Gate Array ◽  
Low Complexity ◽  
Soft Decision ◽  
Coding Gain ◽  
Field Programmable ◽  
Gate Array ◽  
Test Vectors

In this work, we present a new architecture for soft-decision Reed–Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high number of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the location of the errors inside the symbols and the powers of α that identify the positions of the symbols in the frame. Novel schematics for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage are also presented. We also propose novel solutions for the problems that arise when a high number of test vectors is processed. We implemented three decoders: a η = 4 LCC decoder and two decoders that only decode 31 and 60 test vectors of true η = 5 and η = 6 LCC decoders, respectively. For example, our η = 4 decoder requires 29% less look-up tables in Virtex-V Field Programmable Gate Array (FPGA) devices than the best soft-decision RS decoder published to date, while has a 0.07 dB coding gain over that decoder.

NEW APPROACH OF SIGNED BINARY NUMBERS MULTIPLICATION AND ITS IMPLEMENTATION ON FPGA

2021 ◽  
Vol 26 (1) ◽  
pp. 56-68
Author(s):  
Sarifuddin Madenda ◽  
Suryadi Harmanto
Keyword(s):  
Field Programmable Gate Array ◽  
Low Complexity ◽  
Negative Numbers ◽  
New Approach ◽  
New Model ◽  
Proposed Model ◽  
Field Programmable ◽  
Gate Array ◽  
Complexity Algorithm

This paper proposes a new model of signed binary multiplication. This model is formulated mathematically and can handle four types of binary multipliers: signed positive numbers multiplied by signed positive numbers (SPN-by-SPN); signed positive numbers multiplied by signed negative numbers (SPN-by-SNN); signed negative numbers multiplied by signed positive numbers (SNN-by-SPN); and signed negative numbers multiplied by signed negative numbers (SNN-by-SNN). The proposed model has a low complexity algorithm, is easy to implement in software coding and integrated in a hardware FPGA (Field-Programmable Gate Array), and is more powerful compared to the modified Baugh-Wooley's model.

scholarly journals Optimal forgetting: Semantic compression of episodic memories

2020 ◽  
Author(s):  
David G. Nagy ◽  
Balázs Török ◽  
Gergő Orbán
Keyword(s):  
Information Theory ◽  
Resource Constraints ◽  
Human Memory ◽  
Lossy Compression ◽  
Generative Models ◽  
Generative Model ◽  
Complex Data ◽  
Environmental Statistics ◽  
Wide Range ◽  
Memory Resources

AbstractIt has extensively been documented that human memory exhibits a wide range of systematic distortions, which have been associated with resource constraints. Resource constraints on memory can be formalised in the normative framework of lossy compression, however traditional lossy compression algorithms result in qualitatively different distortions to those found in experiments with humans. We argue that the form of distortions is characteristic of relying on a generative model adapted to the environment for compression. We show that this semantic compression framework can provide a unifying explanation of a wide variety of memory phenomena. We harness recent advances in learning deep generative models, that yield powerful tools to approximate generative models of complex data. We use three datasets, chess games, natural text, and hand-drawn sketches, to demonstrate the effects of semantic compression on memory performance. Our model accounts for memory distortions related to domain expertise, gist-based distortions, contextual effects, and delayed recall.Author summaryHuman memory performs surprisingly poorly in many everyday tasks, which have been richly documented in laboratory experiments. While constraints on memory resources necessarily imply a loss of information, it is possible to do well or badly in relation to available memory resources. In this paper we recruit information theory, which establishes how to optimally lose information based on prior and complete knowledge of environmental statistics. For this, we address two challenges. 1, The environmental statistics is not known for the brain, rather these have to be learned over time from limited observations. 2, Information theory does not specify how different distortions of original experiences should be penalised. In this paper we tackle these challenges by assuming that a latent variable generative model of the environment is maintained in semantic memory. We show that compression of experiences through a generative model gives rise to systematic distortions that qualitatively correspond to a diverse range of observations in the experimental literature.

scholarly journals Hardware Considerations for Tensor Implementation and Analysis Using the Field Programmable Gate Array

Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 320 ◽  
Author(s):  
Ian Grout ◽  
Lenore Mullin
Keyword(s):  
Machine Learning ◽  
Field Programmable Gate Array ◽  
Digital Signal ◽  
Learning Systems ◽  
Complex Data ◽  
Outer Product ◽  
Typical Application ◽  
Field Programmable ◽  
Processing Algorithms ◽  
Gate Array

In today’s complex embedded systems targeting internet of things (IoT) applications, there is a greater need for embedded digital signal processing algorithms that can effectively and efficiently process complex data sets. A typical application considered is for use in supervised and unsupervised machine learning systems. With the move towards lower power, portable, and embedded hardware-software platforms that meet the current and future needs for such applications, there is a requirement on the design and development communities to consider different approaches to design realization and implementation. Typical approaches are based on software programmed processors that run the required algorithms on a software operating system. Whilst such approaches are well supported, they can lead to solutions that are not necessarily optimized for a particular problem. A consideration of different approaches to realize a working system is therefore required, and hardware based designs rather than software based designs can provide performance benefits in terms of power consumption and processing speed. In this paper, consideration is given to utilizing the field programmable gate array (FPGA) to implement a combined inner and outer product algorithm in hardware that utilizes the available hardware resources within the FPGA. These products form the basis of tensor analysis operations that underlie the data processing algorithms in many machine learning systems.

FPGA Technology for Implementation in Visual Sensor Networks

2011 ◽  
pp. 293-324
Author(s):  
Wai Chong Chia ◽  
Wing Hong Ngau ◽  
Li-Minn Ang ◽  
Kah Phooi Seng ◽  
Li Wern Chew ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Image Data ◽  
Visual Saliency ◽  
Low Complexity ◽  
Base Station ◽  
Visual Sensor ◽  
Visual Sensor Network ◽  
Visual Sensor Networks ◽  
Field Programmable ◽  
Typical Configuration

A typical configuration of Visual Sensor Network (VSN) usually consists of a set of vision nodes, network motes, and a base station. The vision node is used to capture image data and transmit them to the nearest network mote. Then, the network motes will relay the data within the network until it reaches the base station. Since the vision node is usually small in size and battery-powered, it restricts the resources that can be incorporated onto it. In this chapter, a Field Programmable Gate Array (FPGA) implementation of a low-complexity and strip-based Microprocessor without Interlocked Pipeline Stage (MIPS) architecture is presented. In this case, the image data captured by the vision node is processed in a strip-by-strip manner to reduce the local memory requirement. This allows an image with higher resolution to be captured and processed with the limited resources. In addition, parallel access to the neighbourhood image data is incorporated to improve the accessing speed. Finally, the performance of visual saliency in using the proposed architecture is evaluated.

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