A Clock Stabilization System for CHIME/FRB Outriggers

The Canadian Hydrogen Intensity Mapping Experiment (CHIME) has emerged as the prime telescope for detecting fast radio bursts (FRBs). CHIME/FRB Outriggers will be a dedicated very-long-baseline interferometry (VLBI) instrument consisting of outrigger telescopes at continental baselines working with CHIME and its specialized real-time transient-search backend (CHIME/FRB) to detect and localize FRBs with 50 mas precision. In this paper, we present a minimally invasive clock stabilization system that effectively transfers the CHIME digital backend reference clock from its original GPS-disciplined ovenized crystal oscillator to a passive hydrogen maser. This enables us to combine the long-term stability and absolute time tagging of the GPS clock with the short- and intermediate-term stability of the maser to reduce the clock timing errors between VLBI calibration observations. We validate the system with VLBI-style observations of Cygnus A over a 400 m baseline between CHIME and the CHIME Pathfinder, demonstrating agreement between sky-based and maser-based timing measurements at the 30 ps rms level on timescales ranging from one minute to up to nine days, and meeting the stability requirements for CHIME/FRB Outriggers. In addition, we present an alternate reference clock solution for outrigger stations that lack the infrastructure to support a passive hydrogen maser.

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.52/mg as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40–320 or at data rates from 40Mbps–320Mbps and displays a jitter performance of 520 with a power dissipation of only 11 and an FOM of −235 .

A Fractional Order Control and Correction Strategy for EtherCAT Communication Clock Drift

Ethernet Control Automation Technology (EtherCAT) applies distributed clock (DC) to realize synchronization among different slaves. Due to the influence of the crystal oscillator manufacturing process and environment, there is still synchronization error between reference clock and non-reference clock. To solve the clock synchronization problem, this paper proposes a clock drift compensation algorithm based on the idea of closed-loop control. By designing integer-order proportional integral (IOPI) and fractional-order proportional integral (FOPI) controllers, the synchronization error between slaves can be minimized. The IOPI and FOPI controllers designed in this paper are used to eliminate the drift error. This method improves the synchronization accuracy without bringing too much computational load. The results show that the proposed FOPI controller can effectively reduce the synchronization error with even better performance over the IOPI controller.

A 100 MHz - 1 GHz on-chip-programmable phase-locked-loop

A programmable wide-range PLL has been designed that can provide 100-MHz to 1-GHz rail-to-rail digital clock signal from a 50-MHz reference clock. The architecture is appropriate for low-power design and is also power-efficient. The system is robust against temperature changes so that the stability of the system is guaranteed. Because of the differential configuration of the sub-blocks and using a voltage-controlled oscillator with a 1Ow. gain and a linear transfer function the system has an acceptable noise rejection.

A 100 MHz - 1 GHz on-chip-programmable phase-locked-loop

A programmable wide-range PLL has been designed that can provide 100-MHz to 1-GHz rail-to-rail digital clock signal from a 50-MHz reference clock. The architecture is appropriate for low-power design and is also power-efficient. The system is robust against temperature changes so that the stability of the system is guaranteed. Because of the differential configuration of the sub-blocks and using a voltage-controlled oscillator with a 1Ow. gain and a linear transfer function the system has an acceptable noise rejection.

Clock networks and their sensibility to time-variable gravity signals

<p>High-performance clock networks are considered as a novel tool in geodesy. Today the latest generation of optical clocks approaches a fractional frequency uncertainty of 1.0x10<sup>-18</sup>, which corresponds to about 1.0 cm in height or 0.1 m<sup>2</sup>/s<sup>2</sup> in geopotential. The connected clocks are thus promising to enable “relativistic geodesy” in practice: Gravity potential (or height) differences can be inferred through the ultra-precise comparison of clocks’ frequencies.</p><p>In this study, we will investigate the possibility of high-performance clock networks for detecting time-variable gravity signals. In the past two decades, the satellite gravity mission GRACE, now continued by its follow-on mission, has significantly improved our knowledge on the Earth’s gravity field, especially on its changes over time. However, the results are limited in terms of spatial resolution (about a few hundreds of kilometers) and temporal resolution (standard is one month). Terrestrial clock networks can be used to observe point-wise gravity potential values at locations of interest. By continuously tracking of changes w.r.t. a reference clock, time-series of gravity potential values are obtained, which reveal the gravity variations at these locations. To elaborate this idea, we will address the following research questions:</p><ul><li>Are clock measurements with the accuracy of 10<sup>-18</sup> sensitive enough to time-variable gravity signals? Or what is the requirement on the clock’s performance for detecting time-variable gravity signals?</li> <li>Which kinds of time-variable signals can be “seen” by clocks, the long-term trends (yearly), seasonal variations or short-term changes (weekly/daily)?</li> <li>In which regions might clock networks be sensitive to time-variable gravity signals, in Amazon, Greenland or also in Europe?</li> <li>An “absolute” reference clock is required for a network that should be least affected by gravity variations. Where should it be placed?</li> </ul><p>We gratefully acknowledge the financial support by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Germany’s Excellence Strategy EXC-2123 “QuantumFrontiers” (Project-ID: 390837967). This work is also funded by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) – Project-ID 434617780 – SFB 1464.</p>

A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

A Dispersion Compensation Method Based on Resampling of Modulated Signal for FMCW Lidar

In order to eliminate the nonlinearity in the laser modulation process, the dual-interferometers system is often adopted in the frequency modulation continuous wave (FMCW) laser ranging. However, the dispersion mismatch between the fiber reference interferometer and the measurement interferometer will lead to the decrease in ranging accuracy and resolution. In this paper, a dispersion compensation method based on resampling with a modulated signal is proposed. Since the beat signal of the end face of the delay fiber is not affected by dispersion mismatch, it can be modulated to generate a signal whose phase is proportional to that of the target spatial signal. Then, the modulated signal is regarded as the reference clock to sample the target spatial signal. Thereby, the influence of the dispersion mismatch between the two optical interferometers can be eliminated. In this article, simulation is performed to verify the effect of this method, and an experiment is carried out on the target at the distance of 2.4 m. Experiments show that the full width at half maximum (FWHM) of the distance spectrum after dispersion compensation is consistent with the reflected signal from the end face of the delay fiber, and the standard deviation of multiple measurements reached 10.12 μm.

A Robust and Efficient Fault-Resilient RadHard ADPLL

The high pace emergence in semiconductor technologies and associated application demands have revitalized industries to explore power efficient, stable and fault tolerant digital communication solutions, particularly for time critical applications operating at higher frequency ranges. Thus strengthening low cost CMOS digital design with Radiation Hardened by Design (RHBD) approach can be of paramount significance compared against the high cost Radiation Hard by Process (RHBP) approach. With this motivation, in this paper a novel and robust All-Digital-Phase Locked Loop (ADPLL) design has been developed for frequency synthesis. Our ADPLL design model encompasses multiple novelties and contributions including Feedback-Divider-Less-Counter (FDLC) based ADPLL, predictive phase-frequency detection (PFD), enhanced Time to Digital Converter (TDC) to detect next-edge occurrence of the reference clock that reduces locking period and complexity. The predictive PFD applies a phase-prediction scheme that delays the clock-edges of the reference frequency with a calibrated amount that it always aligned towards the expected frequency clock edge. It makes TDC to be narrow enough to cover the reference and oscillator jitter. Our proposed ADPLL design applied a narrow range converter (TDC) that assist phase-error prediction, correction and phase detection. The reference clock delay facilitates accurate timing relationship estimation with the variable frequency and hence performs retuning of the variable clock to reduce locking period and reduce noise. The ADPLL design has exhibited satisfactory performance for the frequency synthesis with reference frequency of 20MHz and the synthesis frequency of 2.4 GHz meeting radiation hardened features. The simulation results has revealed that the proposed Rad Hard ADPLL design can be a potential solution for space communication systems by maintaining low jitter of 340ps and power consumption of 371.7mW, as the narrow range TDC designed can detect sample radiation induced impulse noise of 20ns, 1mV and correct it.