scholarly journals Why Are Hardware Description Languages Important for Hardware Design Courses?

2021 ◽  
Vol 17 (2) ◽  
pp. 1-16
Author(s):  
Raghad Obeidat ◽  
Hussein Alzoubi
Keyword(s):  
Computer Architecture ◽  
Programming Languages ◽  
Hardware Design ◽  
Logic Design ◽  
Hardware Description Languages ◽  
Computer Engineering ◽  
Hardware Description ◽  
Description Languages ◽  
High Level ◽  
Hardware Designs

Curricula in computer engineering, computer science, and other related fields include several courses about hardware design. Examples of these courses are digital logic design, computer architecture, microprocessors, computer interfacing, hardware design, embedded systems, switching theorem, and others. In order for the students to realize the concepts taught in such courses, practical track should be reinforced along with the theoretical track. Many universities offer to their students labs in which they can practice hardware design. However, students need more than that: they need tools that enable them to design, model, simulate, synthesize, and implement hardware designs. Although high-level programming languages like Java and C++ could be an option, it might be a tedious task to use them for this mission. Fortunately, hardware-description languages (HDLs) have been specifically devised for this purpose. This paper shows some of the great features of HDLs and compare using them with using C++ for illustrating digital concepts through salient examples.

Experiences with High-Level Design and Modelling of Digital Systems

1995 ◽  
Vol 32 (4) ◽  
pp. 333-340
Author(s):  
S. J. Sangwine
Keyword(s):  
Digital Systems ◽  
Hardware Description Languages ◽  
Transversal Filter ◽  
Hardware Description ◽  
Ieee Standard ◽  
Level Design ◽  
Description Languages ◽  
High Level ◽  
The University

Experiences with high-level design and modelling of digital systems Design and modelling of digital systems has been taught at the University of Reading for six years, using Silvar-Lisco HELIX and lately IEEE Standard VHDL hardware description languages. Three exercises have been used throughout this time. These are: modelling of a multiplier-accumulator, design and modelling of a transversal filter, and specification-level modelling of a FIFO.

scholarly journals АНАЛИЗ СРЕДСТВ И ТЕХНОЛОГИЙ РАЗРАБОТКИ FPGA КАК СЕРВИС

2019 ◽  
pp. 88-93
Author(s):  
Инна Николаевна Заризенко ◽  
Артём Евгеньевич Перепелицын
Keyword(s):  
Parallel Processing ◽  
Programming Languages ◽  
High Performance ◽  
Heterogeneous Computing ◽  
Hardware Description Languages ◽  
Labor Costs ◽  
Platform As A Service ◽  
Advantages And Disadvantages ◽  
Hardware Description ◽  
Description Languages

This article has analyzed the most effective integrated development environments from leading programmable logical device (PLD) manufacturers. Heterogeneous calculations and the applicability of a general approach to the description of hardware accelerator designs are considered. An analytical review of the use of the OpenCL language in the construction of high-performance FPGA-based solutions is performed. The features of OpenCL language usage for heterogeneous computing for FPGA-based accelerators are discussed. The experience of a unified description of projects for solutions based on CPU, GPU, signal processors and FPGA is analyzed. The advantages of using such a description for tasks that perform parallel processing are shown. Differences in productivity and labor costs for developing FPHA systems with parallel data processing for hardware description languages and OpenCL language are shown. The results of comparing commercially available solutions for building services with FPGA accelerators are presented. The advantages of the Xilinx platform and tools for building an FPGA service are discussed. The stages of creating solutions based on FaaS are proposed. Some FaaS related tasks are listed and development trends are discussed. The SDAccel platform of the Xilinx SDx family is considered, as well as the possible role of these tools in creating the FPGA computing platform as a service. An example of using SDAccel to develop parallel processing based on FPGA is given. The advantages and disadvantages of the use of hardware description languages with such design automation tools are discussed. The results of comparing the performance of the simulation speed of the system described with the use of programming languages and hardware description languages are presented. The advantages of modeling complex systems are discussed, especially for testing solutions involving the processing of tens of gigabytes of data and the impossibility of creating truncated test sets. Based on practical experience, the characteristics of development environments, including undocumented ones, are formulated.

scholarly journals Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

2017 ◽  
Vol 7 (4) ◽  
pp. 2192
Author(s):  
Nejmeddine Alimi ◽  
Younes Lahbib ◽  
Mohsen Machhout ◽  
Rached Tourki
Keyword(s):  
Good Evidence ◽  
Modular Arithmetic ◽  
Functional Verification ◽  
Hardware Description Languages ◽  
Abstraction Level ◽  
Hardware Description ◽  
Multi Level ◽  
Description Languages ◽  
High Level ◽  
Real Challenge

Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability.

A calculus for hardware description

2010 ◽  
Vol 21 (1) ◽  
pp. 21-58 ◽  
Author(s):  
SUNGWOO PARK ◽  
HYEONSEUNG IM
Keyword(s):  
Formal Semantics ◽  
Type System ◽  
Hardware Description Languages ◽  
Linear Type ◽  
Function Type ◽  
Hardware Description ◽  
Description Languages ◽  
High Level ◽  
Structural Descriptions ◽  
Hardware Circuit

AbstractIn efforts to overcome the complexity of the syntax and the lack of formal semantics of conventional hardware description languages, a number of functional hardware description languages have been developed. Like conventional hardware description languages, however, functional hardware description languages eventually convert all source programs into netlists, which describe wire connections in hardware circuits at the lowest level and conceal all high-level descriptions written into source programs. We develop a calculus, called lλ (linear lambda), which may serve as an intermediate functional language just above netlists in the hierarchy of hardware description languages. In order to support higher-order functions, lλ uses a linear type system, which enforces the linear use of variables of function type. The translation of lλ into structural descriptions of hardware circuits is sound and complete in the sense that it maps expressions only to realizable hardware circuits, and that every realizable hardware circuit has a corresponding expression in lλ. To illustrate the use of lλ as a practical intermediate language for hardware description, we design a simple hardware description language that extends lλ with polymorphism, and use it to implement a fast Fourier transform circuit and a bitonic sorting network.

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