Incorporating a 4x4 Keypad in a Simple Digital Clock

2013 ◽  
Vol 433-435 ◽  
pp. 1438-1447
Author(s):  
Wan Fu Huang

Most simple digital clocks use a push button to increment time reading for time adjustment. It is often time consuming. This paper suggests adding a four-by-four keypad to adjust each single time digit. The required valid 4x4 keypad key set for each time digit is predefined in the circuit design. Pressing a prohibited key would neither generate any function nor affect the operation of the digital clock. The system prototype circuit design was based on Verilog hardware description language and implemented on an EVS6 Boardan FPGA lab board. With the proposed design, adjusting time on a digital clock is quick and easy.

Author(s):  
Satya Ranjan Sahu ◽  
Bandan Kumar Bhoi ◽  
Manoranjan Pradhan

This paper presents the design of improved redundant binary adder (IRBA) by utilizing positive–negative encoding rules in FPGA platform. The proposed design deals with inverted encoding of negative binary (IEN) and positive binary number to get addition result using readily available standard hardware module. The Verilog hardware description language is used as design entry for synthesis of the proposed architecture in Xilinx ISE Desisn Suite 14.4 software. This structure is realized on Vertex-4 xc4vfx12-12sf363 FPGA device. The proposed IRBA is found to be time efficient in comparison with the performance parameters such as propagation delay and area over previous reported architecture.


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