Blind Estimation of Long Code DSSS Signal Based on Subspace Tracking

2014 ◽  
Vol 484-485 ◽  
pp. 976-981 ◽  
Author(s):  
Chao Ma ◽  
Li Min Zhang ◽  
Jian Xiong Wang

Aiming at solving the blind estimation problem of dispreading spectrum sequence under low SNR, a spread-spectrum estimation algorithm based subspace tracking is studied in this paper. This method avoids the direct eigen decomposition, using the sliding window technique to obtain the code synchronization, then use segmentation subspace tracking method estimate spreading sequence and splice in a certain order to achieve pseudo-code blind estimation. The results show that the algorithm can complete the accurate estimation of PN code sequence in low SNR conditions, reduce the amount of data storage and be easy hardware implementation

2020 ◽  
Vol 2020 ◽  
pp. 1-10
Author(s):  
Shan-Shan Li ◽  
Jian Zhou ◽  
Xuan Wang

Aiming at the shortcomings of traditional broadcast transmitter noise test methods, such as low efficiency, inconvenient data storage, and high requirements for testers, a dynamic online test method for transmitter noise is proposed. The principle of system composition and test method is given. The transmitter noise is real-time changing. The Voice Active Detection (VAD) noise estimation algorithm cannot track the transmitter noise change in real time. This paper proposes a combined noise estimation algorithm for VAD and dynamic estimation. By setting the threshold of the double-threshold VAD detection to be low, it can accurately detect the silent segment. The silent segment is used as a noise signal for noise estimation. For the nonsilent segment detected by the VAD, a minimum value search dynamic spectrum estimation algorithm based on the existence probability of the speech (IMCRA) is used for noise estimation. Transmitter noise is measured by calculating the noise figure (NF).The test method collects the input and output data of the transmitter in real time, which has better accuracy and real-time performance, and the feasibility of the method is verified by experimental simulation.


2017 ◽  
Vol 10 (2) ◽  
pp. 141-148
Author(s):  
Abdelmadjid Maali ◽  
Geneviève Baudoin ◽  
Ammar Mesloub

In this paper, we propose a novel energy detection (ED) receiver architecture combined with time-of-arrival (TOA) estimation algorithm, compliant to the IEEE 802.15.4a standard. The architecture is based on double overlapping integrators and a sliding correlator. It exploits a series of ternary preamble sequences with perfect autocorrelation property. This property ensures coding gain, which allows an accurate estimation of power delay profile (PDP). To improve TOA estimation, the interpolation of PDP samples is proposed and the architecture is validated by using an ultra-wideband signals measurements platform. These measurements are carried out in line-of-sight and non-line-of-sight multipath environments. The experimental results show that the ranging performances obtained by the proposed architecture are higher than those obtained by the conventional architecture based on a single-integrator in both LOS and NLOS environments.


Author(s):  
Katyayani Kashayp ◽  
Kandarpa Kumar Sarma ◽  
Manash Pratim Sarma

Spread spectrum modulation (SSM) finds important place in wireless communication primarily due to its application in Code Division Multiple Access (CDMA) and its effectiveness in channels fill with noise like signals. One of the critical issues in such modulation is the generation of spreading sequence. This chapter presents a design of chaotic spreading sequence for application in a Direct Sequence Spread Spectrum (DS SS) system configured for a faded wireless channel. Enhancing the security of data transmission is a prime issue which can better be addressed with a chaotic sequence. Generation and application of chaotic sequence is done and a comparison with Gold sequence is presented which clearly indicates achieving better performance with simplicity of design. Again a multiplierless logistic map sequence is generated for lower power requirements than the existing one. The primary blocks of the system are implemented using Verilog and the performances noted. Experimental results show that the proposed system is an efficient sequence generator suitable for wideband systems demonstrating lower BER levels, computational time and power requirements compared to traditional LFSR based approaches.


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