A High Rate Parallel Operation Encryption Card Design Base on FPGA
2014 ◽
Vol 668-669
◽
pp. 783-786
Keyword(s):
A design of encryption cards controlling multiple cipher chips’ high-rate parallel operation based on FPGA is proposed in this paper. According to the design method, we can achieve that multiple encryption card operates encryption in parallel way, which can improve the encryption and decryption rate of the encryption card without enhancing the performance of encryption chip, moreover, increase the key generation rate and management level of the key management system.
2014 ◽
Vol 644-650
◽
pp. 1907-1910
2013 ◽
Vol 748
◽
pp. 1244-1250
Keyword(s):
2011 ◽
Vol 121-126
◽
pp. 1120-1124
2002 ◽
Vol 46
(3)
◽
pp. 367-371
Keyword(s):
2014 ◽
Vol 539
◽
pp. 669-673