A Verification Method of Multi-Threaded Processor Based on Tree-Structure

2011 ◽  
Vol 403-408 ◽  
pp. 1865-1868
Author(s):  
Pei Jun Ma ◽  
Meng Liu ◽  
Kang Li ◽  
Jiang Yi Shi
Keyword(s):  
Tree Structure ◽  
Functional Verification ◽  
Feedback Information ◽  
Verification Method ◽  
Functional Coverage ◽  
Coverage Model ◽  
Speed Up ◽  
Structure Instruction

A method based on tree-structure for verifying a multi-threading processor is described in this paper. In this method, instructions are classified according to tree-structure, instruction stream is generated by hierarchical random and the tree-structure is pruned by feedback information of functional coverage model. Results show that this method can speed up the convergence of the coverage and supply effective functional verification for micro-engine.

scholarly journals RHPTree—Risk Hierarchical Pattern Tree for Scalable Long Pattern Mining

2022 ◽  
Vol 16 (4) ◽  
pp. 1-33
Author(s):  
Danlu Liu ◽  
Yu Li ◽  
William Baskett ◽  
Dan Lin ◽  
Chi-Ren Shyu
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Pattern Mining ◽  
Tree Structure ◽  
Research Initiative ◽  
Speed Up ◽  
Dynamic Tree ◽  
Significant Patterns ◽  
Search Approach ◽  
Hierarchical Pattern

Risk patterns are crucial in biomedical research and have served as an important factor in precision health and disease prevention. Despite recent development in parallel and high-performance computing, existing risk pattern mining methods still struggle with problems caused by large-scale datasets, such as redundant candidate generation, inability to discover long significant patterns, and prolonged post pattern filtering. In this article, we propose a novel dynamic tree structure, Risk Hierarchical Pattern Tree (RHPTree), and a top-down search method, RHPSearch, which are capable of efficiently analyzing a large volume of data and overcoming the limitations of previous works. The dynamic nature of the RHPTree avoids costly tree reconstruction for the iterative search process and dataset updates. We also introduce two specialized search methods, the extended target search (RHPSearch-TS) and the parallel search approach (RHPSearch-SD), to further speed up the retrieval of certain items of interest. Experiments on both UCI machine learning datasets and sampled datasets of the Simons Foundation Autism Research Initiative (SFARI)—Simon’s Simplex Collection (SSC) datasets demonstrate that our method is not only faster but also more effective in identifying comprehensive long risk patterns than existing works. Moreover, the proposed new tree structure is generic and applicable to other pattern mining problems.

scholarly journals A Specification-Based Semi-Formal Functional Verification Method by a Stage Transition Graph Model

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 14947-14958
Author(s):  
Zhao Lv ◽  
Shuming Chen ◽  
Tingrong Zhang ◽  
Yaohua Wang
Keyword(s):  
Graph Model ◽  
Functional Verification ◽  
Transition Graph ◽  
Verification Method ◽  
Stage Transition

Adaptive Genetic Algorithm Verification Technology Driven by Functional Coverage

2014 ◽  
Vol 644-650 ◽  
pp. 2264-2268
Author(s):  
Jing Kai Shi ◽  
Jian Lang Wu ◽  
Yi Bin Wang
Keyword(s):  
Genetic Algorithm ◽  
Functional Verification ◽  
Adaptive Genetic Algorithm ◽  
Test Vector ◽  
Efficient Test ◽  
Functional Coverage ◽  
Vector Generation ◽  
Test Points ◽  
Efficiency And Reliability ◽  
Algorithm Verification

With the increasing of Chip integration and operation velocity, the gap between validation and design is becoming larger and larger. Now the focus is on generating efficient test vector. Different weights are appropriately set based on the relationships between the code logical depth of function test points and the test points covered by a test vector. A test vector generation method based on adaptive genetic algorithm is proposed. The experimental results show that the method can reduce the time of writing constraint files, auto-generate a stimulation, which is more efficient and targeted, and improve the efficiency and reliability of the chip functional verification.

VERIFICATION OF DATAFLOW SCHEDULING

2008 ◽  
Vol 18 (06) ◽  
pp. 737-758
Author(s):  
TSUNG-HSI CHIANG ◽  
LAN-RONG DUNG
Keyword(s):  
Formal Verification ◽  
Petri Net ◽  
Register Transfer Level ◽  
Functional Verification ◽  
Model Checker ◽  
Symbolic Model ◽  
Verification Method ◽  
Level Design ◽  
High Level ◽  
Design Scheduling

This paper presents the formal verification method for high-level synthesis (HLS) to detect design errors of dataflow algorithms by using Petri Net (PN) and symbolic-model-verifier (SMV) techniques. Formal verification in high-level design means architecture verification, which is different from functional verification in register transfer level (RTL). Generally, dataflow algorithms need algorithmic transformations to achieve optimal goals and also need design scheduling to allocate processor resources before mapping on a silicon. However, algorithmic transformations and design scheduling are error-prone. In order to detect high-level faults, high-level verification is applied to verify the synthesis results in HLS. Instead of applying Boolean algebra in traditional verification, this paper adopts both Petri Net theory and SMV model checker to verify the correctness of the synthesis results of the high-level dataflow designs. In the proposed hybrid verification method, a high-level design or DUV (design-under-verification) is first transformed into a Petri Net model. Then, Petri Net theory is applied to check the correctness of its algorithmic transformations of HLS, and the SMV model checker is used to verify the correctness of the design scheduling. We presented two approaches to realize the proposed verification method and concluded the best one who outperforms the other in terms of processing speed and resource usage.

External Memory Interface Verification Based on VMM

2014 ◽  
Vol 981 ◽  
pp. 103-106
Author(s):  
Rui Xu ◽  
Zhan Peng Jiang ◽  
Chang Chun Dong ◽  
Xue Bin Lu
Keyword(s):  
Complex Function ◽  
External Memory ◽  
Functional Verification ◽  
Verification Method ◽  
Coverage Control ◽  
Memory Interface ◽  
Verification Methodology

With the growth of the scale of SoC, function verification becomes more and more complicated. Traditional functional verification method is confronted with some challenges. This paper achieves coverage-driven, constrained-randomization and assertion verification methodology based on SystemVerilog and VMM, to build verification platform by taking example of EMI (external memory interface). As result of verification, we can monitor coverage, control the platform, optimize testbench and testcase, finish function coverage 100%. These applications can simplify complex function verification, improve the platform reuse, and meet the needs of chip verification.

scholarly journals Simulation-Based Hardware Verification with a Graph-Based Specification

2018 ◽  
Vol 2018 ◽  
pp. 1-10
Author(s):  
Zhao Lv ◽  
Shuming Chen ◽  
Yaohua Wang
Keyword(s):  
Pattern Generation ◽  
Ease Of Use ◽  
Hardware Verification ◽  
Verification Method ◽  
Functional Coverage ◽  
Coverage Criterion ◽  
Simulation Based ◽  
Functional Correctness ◽  
Test Vectors ◽  
Verification Techniques

Simulation-based verification continues to be the primary technique for hardware verification due to its scalability and ease of use; however, it lacks exhaustiveness. Although formal verification techniques can exhaustively prove functional correctness, they are limited in terms of the scale of their design due to the state-explosion problem. Alternatively, semiformal approaches can involve a compromise between scalability, exhaustiveness, and resource costs. Therefore, we propose an event-driven flow graph-based specification, which can describe the cycle-accurate functional behaviors without the exploration of whole state space. To efficiently generate input sequences according to the proposed specification, we introduce a functional automatic test pattern generation (ATPG) approach, which involves the proposed intelligent redundancy-reduction strategy to solve problems of random test vectors. We also proposed functional coverage criterion based on the formal specification to support a more reliable measure of verification. We implement a verification platform based on the proposed semiformal approach and compare the proposed semiformal approach with the constrained randomized test (CRT) approach. The experiment results show that the proposed semiformal verification method ensures a more exhaustive and effective exploration of the functional correctness of designs under verification (DUVs).

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