Full Scan Structure Application in the Design of 16 Bit MCU
2014 ◽
Vol 981
◽
pp. 78-81
◽
A design project of 16 bit RISC MCU with full scan structure by the tool of SYNOPSYSTM DFT COMPILER. The flip-flops can be linked into the chains; the memory modules in the MCU were tested by the technology of BIST; and the circuits were tested by the test vectors by ATPG. The chip test circuit include 8 chains, and cover rate can reach at 99.20%.
2009 ◽
Vol E92-A
(12)
◽
pp. 3128-3135
Keyword(s):
2018 ◽
Vol 12
(2)
◽
pp. 146
◽
Keyword(s):
2020 ◽
Vol 3
(331)
◽
pp. 118-126
2020 ◽
Vol 4
(4)
◽
pp. 143-150