Background:
Output polarity of the sub-function is generally considered to reduce the area
and power of a circuit at the two-level realization. Along with area and power, the power-density is also
one of the significant parameter which needs to be consider, because power-density directly converges
to circuit temperature. More than 50% of the modern day integrated circuits are damaged due to
excessive overheating.
Methods:
This work demonstrates the impact of efficient power density based logic synthesis (in the
form of suitable polarity selection of sub-function of Programmable Logic Arrays (PLAs) for its multilevel
realization) for the reduction of temperature. Two-level PLA optimization using output polarity
selection is considered first and compared with other existing techniques and then And-Invert Graphs
(AIG) based multi-level realization has been considered to overcome the redundant solution generated
in two-level synthesis. AIG nodes and associated power dissipation can be reduced by rewriting,
refactoring and balancing technique. Reduction of nodes leads to the reduction of the area but on the
contrary increases power and power density of the circuit. A meta-heuristic search approach i.e., Nondominated
Sorting Genetic Algorithm-II (NSGA-II) is proposed to select the suitable output polarity of
PLA sub-functions for its optimal realization.
Results:
Best power density based solution saves up to 8.29% power density compared to ‘espresso –
dopo’ based solutions. Around 9.57% saving in area and 9.67% saving in power (switching activity) are
obtained with respect to ‘espresso’ based solution using NSGA-II.
Conclusion:
Suitable output polarity realized circuit is converted into multi-level AIG structure and
synthesized to overcome the redundant solution at the two-level circuit. It is observed that with the
increase in power density, the temperature of a particular circuit is also increases.
CLS-SMT: Bringing Together Combinatory Logic Synthesis and Satisfiability Modulo Theories