Engineering Theories with Z3

10.29007/x7b4 ◽  
2018 ◽  
Author(s):  
Nikolaj Bjorner
Keyword(s):  
Satisfiability Modulo Theories ◽  
Smt Solver ◽  
Testing Tools ◽  
Software And Hardware ◽  
Design And Testing

Modern Satisfiability Modulo Theories (SMT)solvers are fundamental to many programanalysis, verification, design and testing tools. They are a goodfit for the domain of software and hardware engineering becausethey support many domains that are commonly used by the tools.The meaning of domains are captured by theories that can beaxiomatized or supported by efficient <i>theory solvers</i>.Nevertheless, not all domains are handled by all solvers andmany domains and theories will never be native to any solver.We here explore different theories that extend MicrosoftResearch's SMT solver Z3's basicsupport. Some can be directly encoded or axiomatized,others make use of user theory plug-ins.Plug-ins are a powerful way for tools to supply their custom domains.

scholarly journals Scheduling Optimization of Time-Triggered Cyber-Physical Systems Based on Fuzzy-Controlled QPSO and SMT Solver

Energies ◽  
2020 ◽  
Vol 13 (3) ◽  
pp. 668
Author(s):  
Jie Jian ◽  
Lide Wang ◽  
Huang Chen ◽  
Xiaobo Nie
Keyword(s):  
Scheduling Algorithm ◽  
Cyber Physical Systems ◽  
Satisfiability Modulo Theories ◽  
Random Mutation ◽  
Physical Systems ◽  
Smt Solver ◽  
Time Requirements ◽  
Adaptive Adjustment ◽  
Periodic Traffic ◽  
Cost Efficient

The time-triggered communication paradigm is a cost-efficient way to meet the real-time requirements of cyber-physical systems. It is a non-deterministic polynomial NP-complete problem for multi-hop networks and non-strictly periodic traffic. A two-level scheduling approach is proposed to simplify the complexity during optimization. In the first level, a fuzzy-controlled quantum-behaved particle swarm optimization (FQPSO) algorithm is proposed to optimize the scheduling performance by assigning time-triggered frame instances to the basic periods of each link. In order to prevent population from high aggregation, a random mutation mechanism is used to disturb particles at the aggregation point and enhance the diversity at later stages. Fuzzy logic is introduced and well designed to realize a dynamic adaptive adjustment of the contraction–expansion coefficient and mutation rate in FQPSO. In the second level, we use an improved Satisfiability Modulo Theories (SMT) scheduling algorithm to solve the collision-free and temporal constraints. A schedulability ranking method is proposed to accelerate the computation of the SMT-based incremental scheduler. Our approach can co-optimize the jitter and load balance of communication for an off-line schedule. The experiments show that the proposed approach can improve the performance of the scheduling table, reduce the optimization time, and reserve space for incremental messages.

scholarly journals Representing hybrid automata by action language modulo theories

2017 ◽  
Vol 17 (5-6) ◽  
pp. 924-941 ◽  
Author(s):  
JOOHYUNG LEE ◽  
NIKHIL LONEY ◽  
YUNSONG MENG
Keyword(s):  
Differential Equations ◽  
Ordinary Differential Equations ◽  
Satisfiability Modulo Theories ◽  
Prototype System ◽  
Hybrid Automata ◽  
Action Languages ◽  
Smt Solver ◽  
Action Language ◽  
Linear Hybrid Automata ◽  
Answer Set

AbstractBoth hybrid automata and action languages are formalisms for describing the evolution of dynamic systems. This paper establishes a formal relationship between them. We show how to succinctly represent hybrid automata in an action language which in turn is defined as a high-level notation for answer set programming modulo theories—an extension of answer set programs to the first-order level similar to the way satisfiability modulo theories (SMT) extends propositional satisfiability (SAT). We first show how to represent linear hybrid automata with convex invariants by an action language modulo theories. A further translation into SMT allows for computing them using SMT solvers that support arithmetic over reals. Next, we extend the representation to the general class of non-linear hybrid automata allowing even non-convex invariants. We represent them by an action language modulo ordinary differential equations, which can be compiled into satisfiability modulo ordinary differential equations. We present a prototype systemcplus2aspmtbased on these translations, which allows for a succinct representation of hybrid transition systems that can be computed effectively by the state-of-the-art SMT solverdReal.

scholarly journals Learning Probabilistic Termination Proofs

2021 ◽  
pp. 3-26
Author(s):  
Alessandro Abate ◽  
Mirco Giacobbe ◽  
Diptarko Roy
Keyword(s):  
Learning Strategy ◽  
Source Code ◽  
Satisfiability Modulo Theories ◽  
Smt Solver ◽  
Execution Traces ◽  
State Dependent ◽  
Polynomial Programs ◽  
Continuous State ◽  
Guided Inductive ◽  
Probabilistic Programs

AbstractWe present the first machine learning approach to the termination analysis of probabilistic programs. Ranking supermartingales (RSMs) prove that probabilistic programs halt, in expectation, within a finite number of steps. While previously RSMs were directly synthesised from source code, our method learns them from sampled execution traces. We introduce the neural ranking supermartingale: we let a neural network fit an RSM over execution traces and then we verify it over the source code using satisfiability modulo theories (SMT); if the latter step produces a counterexample, we generate from it new sample traces and repeat learning in a counterexample-guided inductive synthesis loop, until the SMT solver confirms the validity of the RSM. The result is thus a sound witness of probabilistic termination. Our learning strategy is agnostic to the source code and its verification counterpart supports the widest range of probabilistic single-loop programs that any existing tool can handle to date. We demonstrate the efficacy of our method over a range of benchmarks that include linear and polynomial programs with discrete, continuous, state-dependent, multi-variate, hierarchical distributions, and distributions with undefined moments.

A Path-Based Equivalence Checking Method Between System Level and RTL Descriptions Using Machine Learning

2020 ◽  
pp. 2150074
Author(s):  
Jian Hu ◽  
Yongyang Hu ◽  
Qi Lv ◽  
Wentao Wang ◽  
Guanwu Wang ◽  
...  
Keyword(s):  
Machine Learning ◽  
Digital Design ◽  
Satisfiability Modulo Theories ◽  
System Level ◽  
Equivalence Checking ◽  
Smt Solver ◽  
Efficiency And Effectiveness ◽  
Finite State ◽  
Level Model ◽  
High Level

The growing complexity of modern digital design makes designers shift toward starting design exploration using high-level languages, and generating register transfer level (RTL) design from system level modeling (SLM) using high-level synthesis tools or manual transformation. Unfortunately, this translation process is very complex and error prone. The most important verification task is to check whether the RTL implementation is indeed equivalent to the system-level model. Equivalence checking is critical to ensure that the synthesized RTL conforms to its SLM specification. In this paper, we propose a novel path-based sequential equivalence checking method to validate the transformed RTL description against its corresponding SLM description. We represent the original SLM and the transformed RTL descriptions using Finite state machines with datapath (FSMD) and compare the path-pairs of the FSMD to obtain the equivalence of the designs. Then we recognize the corresponding path-pairs from all the generated paths of FSMD with Machine learning (ML) technique, and compare the recognized path-pairs by symbolic simulation and a satisfiability modulo theories (SMT) solver. Our method can handle designs without mapping information and improve the efficiency of the state-of-the-art path-based equivalence checking methods. The promising experiments on representative benchmarks indicate the efficiency and effectiveness of our method.

scholarly journals Concurrency Debugging with MaxSMT

2019 ◽  
Vol 33 ◽  
pp. 1608-1616 ◽  
Author(s):  
Miguel Terra-Neves ◽  
Nuno Machado ◽  
Ines Lynce ◽  
Vasco Manquinho
Keyword(s):  
Satisfiability Modulo Theories ◽  
Huge Number ◽  
Sequential Programs ◽  
Concurrency Bugs ◽  
Maximum Satisfiability ◽  
Smt Solver ◽  
Root Cause ◽  
Recent Approach ◽  
Sat Solver ◽  
Current Maximum

Current Maximum Satisfiability (MaxSAT) algorithms based on successive calls to a powerful Satisfiability (SAT) solver are now able to solve real-world instances in many application domains. Moreover, replacing the SAT solver with a Satisfiability Modulo Theories (SMT) solver enables effective MaxSMT algorithms. However, MaxSMT has seldom been used in debugging multi-threaded software.Multi-threaded programs are usually non-deterministic due to the huge number of possible thread operation schedules, which makes them much harder to debug than sequential programs. A recent approach to isolate the root cause of concurrency bugs in multi-threaded software is to produce a report that shows the differences between a failing and a non-failing execution. However, since they rely solely on heuristics, these reports can be unnecessarily large. Hence, reports may contain operations that are not relevant to the bug’s occurrence.This paper proposes the use of MaxSMT for the generation of minimal reports for multi-threaded software with concurrency bugs. The proposed techniques report situations that the existing techniques are not able to identify. Experimental results show that using MaxSMT can significantly improve the accuracy of the generated reports and, consequently, their usefulness in debugging the root cause of concurrency bugs.

Semantic subtyping with an SMT solver

2012 ◽  
Vol 22 (1) ◽  
pp. 31-105 ◽  
Author(s):  
GAVIN M. BIERMAN ◽  
ANDREW D. GORDON ◽  
CĂTĂLIN HRIŢCU ◽  
DAVID LANGWORTHY
Keyword(s):  
Specific Model ◽  
Satisfiability Modulo Theories ◽  
The Novel ◽  
Dynamic Tests ◽  
Boolean Expression ◽  
Type Checking ◽  
Smt Solver ◽  
First Order ◽  
A Value ◽  
Type Test

AbstractWe study a first-order functional language with the novel combination of the ideas of refinement type (the subset of a type to satisfy a Boolean expression) and type-test (a Boolean expression testing whether a value belongs to a type). Our core calculus can express a rich variety of typing idioms; for example, intersection, union, negation, singleton, nullable, variant, and algebraic types are all derivable. We formulate a semantics in which expressions denote terms, and types are interpreted as first-order logic formulas. Subtyping is defined as valid implication between the semantics of types. The formulas are interpreted in a specific model that we axiomatize using standard first-order theories. On this basis, we present a novel type-checking algorithm able to eliminate many dynamic tests and to detect many errors statically. The key idea is to rely on a Satisfiability Modulo Theories solver to compute subtyping efficiently. Moreover, using a satisfiability modulo theories solver allows us to show the uniqueness of normal forms for non-deterministic expressions, provide precise counterexamples when type-checking fails, detect empty types, and compute instances of types statically and at run-time.

scholarly journals Counterexample-Driven Genetic Programming: Stochastic Synthesis of Provably Correct Programs

2018 ◽  
Author(s):  
Krzysztof Krawiec ◽  
Iwo Błądek ◽  
Jerry Swan ◽  
John H. Drake
Keyword(s):  
Genetic Programming ◽  
State Of The Art ◽  
Satisfiability Modulo Theories ◽  
Formal Specifications ◽  
Training Set ◽  
Effective Technique ◽  
Smt Solver ◽  
Evaluation Phase ◽  
Training Examples ◽  
Output Behavior

Genetic programming is an effective technique for inductive synthesis of programs from tests, i.e. training examples of desired input-output behavior. Programs synthesized in this way are not guaranteed to generalize beyond the training set, which is unacceptable in many applications. We present Counterexample-Driven Genetic Programming (CDGP) that employs evolutionary search to synthesize provably correct programs from formal specifications. CDGP employs a Satisfiability Modulo Theories (SMT) solver to formally verify programs in the evaluation phase. A failed verification produces counterexamples that are in turn used to calculate fitness and thereby drive the search process. When compared with a range of approaches on a suite of state-of-the-art specification-based synthesis benchmarks, CDGP systematically outperforms them, typically synthesizing correct programs faster and using fewer tests.

scholarly journals Syntax-Guided Quantifier Instantiation

2021 ◽  
pp. 145-163
Author(s):  
Aina Niemetz ◽  
Mathias Preiner ◽  
Andrew Reynolds ◽  
Clark Barrett ◽  
Cesare Tinelli
Keyword(s):  
State Of The Art ◽  
Satisfiability Modulo Theories ◽  
Floating Point ◽  
New Approach ◽  
Smt Solver ◽  
Floating Point Arithmetic ◽  
Novel Approach ◽  
Non Linear ◽  
Quantifier Instantiation ◽  
Point Arithmetic

AbstractThis paper presents a novel approach for quantifier instantiation in Satisfiability Modulo Theories (SMT) that leverages syntax-guided synthesis (SyGuS) to choose instantiation terms. It targets quantified constraints over background theories such as (non)linear integer, reals and floating-point arithmetic, bit-vectors, and their combinations. Unlike previous approaches for quantifier instantiation in these domains which rely on theory-specific strategies, the new approach can be applied to any (combined) theory, when provided with a grammar for instantiation terms for all sorts in the theory. We implement syntax-guided instantiation in the SMT solver CVC4, leveraging its support for enumerative SyGuS. Our experiments demonstrate the versatility of the approach, showing that it is competitive with or exceeds the performance of state-of-the-art solvers on a range of background theories.

Leveraging Control Flow Knowledge in SMT Solving of Program Verification

2021 ◽  
Vol 30 (4) ◽  
pp. 1-26
Author(s):  
Jianhui Chen ◽  
Fei He
Keyword(s):  
Program Verification ◽  
Search Space ◽  
General Purpose ◽  
Control Flow ◽  
Satisfiability Modulo Theories ◽  
Useful Knowledge ◽  
Smt Solver ◽  
Software Analysis ◽  
Smt Solving ◽  
Novel Approach

Satisfiability modulo theories (SMT) solvers have been widely applied as the reasoning engine for diverse software analysis and verification technologies. The efficiency of the SMT solver has significant effects on the performance of these technologies. However, current SMT solvers are designed for the general purpose of constraint solving. Lots of useful knowledge of programs cannot be utilized during SMT solving. As a result, the SMT solver may spend much effort to explore redundant search space. In this article, we propose a novel approach to utilizing control-flow knowledge in SMT solving. With this technique, the search space can be considerably reduced, and the efficiency of SMT solving is observably improved. We conducted extensive experiments on credible benchmarks. The results show significant improvements of our approach.

scholarly journals Relaxing non-interference requirements in parallel plans

2019 ◽  
Author(s):  
Miquel Bofill ◽  
Joan Espasa ◽  
Mateu Villaret
Keyword(s):  
Satisfiability Modulo Theories ◽  
Semantic Interference ◽  
Smt Solver ◽  
Semantic Notion ◽  
The Many

Abstract The aim of being able to reason about quantities, time or space has been the main objective of the many efforts on the integration of propositional planning with extensions to handle different theories. Planning modulo theories (PMTs) are an approximation inspired by satisfiability modulo theories (SMTs) that generalize the integration of arbitrary theories with propositional planning. Parallel plans are crucial to reduce plan lengths and hence the time needed to reach a feasible plan in many approaches. Parallelization of actions relies on the notion of (non-)interference, which is usually determined syntactically at compile time. In this paper we define a semantic notion of interference between actions in PMT. Apart from being strictly stronger than any syntactic notion of interference, we show how semantic interference can be easily and efficiently checked by calling an off-the-shelf SMT solver at compile time, constituting a technique orthogonal to the solving method.

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