Design of Interplanetary Observation Terminal based on All Programmable System-on-Chip

2021 ◽  
Author(s):  
Haonan Jin ◽  
Lesheng He ◽  
Liang Dong ◽  
Yongliang Tan ◽  
Qingyang Kong
Keyword(s):  
Solar Wind ◽  
Human Life ◽  
Average Power ◽  
Experimental Tests ◽  
System On Chip ◽  
High Time Resolution ◽  
Processing Scheme ◽  
Gigabit Ethernet ◽  
System Memory ◽  
On Chip

The drastic changes in the solar wind will cause serious harm to human life. Monitoring interplanetary scintillation (IPS) can predict solar wind activity, thereby effectively reducing the harm caused by space weather. Aiming at the problem of the lack of the ability to observe IPS phenomenon of the 40-meter radio telescope at the Yunnan Astronomical Observatory of China in the frequency band around 300MHz, an IPS real-time acquisition and processing scheme based on all programmable system-on-chip(APSoC) was proposed. The system calculates the average power of 10ms IPS signal in PL-side and transmits it to the system memory through AXI4 bus. PS-side reads the data, takes logarithms, packages it, and finally transmits it to the LabVIEW host computer through gigabit Ethernet UDP mode for display and storage. Experimental tests show that the system functions correctly, and the PL-side power consumption is only 1.955 W, with a high time resolution of 10ms, and no data is lost in 24 hours of continuous observation, with good stability. The system has certain application value in IPS observation.

scholarly journals A Hardware Accelerator for the Inference of a Convolutional Neural network

2019 ◽  
Vol 30 (1) ◽  
pp. 107-116 ◽  
Author(s):  
Edwin González ◽  
Walter D. Villamizar Luna ◽  
Carlos Augusto Fajardo Ariza
Keyword(s):  
Field Programmable Gate Array ◽  
System On Chip ◽  
Software Implementation ◽  
Hardware Accelerator ◽  
Processing Scheme ◽  
Field Programmable ◽  
Computationally Intensive ◽  
On Chip ◽  
Memory Resources ◽  
Better Than

Convolutional Neural Networks (CNNs) are becoming increasingly popular in deep learning applications, e.g. image classification, speech recognition, medicine, to name a few. However, the CNN inference is computationally intensive and demanding a large among of memory resources. In this work is proposed a CNN inference hardware accelerator, which was implemented in a co-processing scheme. The aim is to reduce the hardware resources and achieve the better possible throughput. The design was implemented in the Digilent Arty Z7-20 development board, which is based on System on Chip (SoC) Zynq-7000 of Xilinx. Our implementation achieved a  of accuracy for the MNIST database using only 12-bits fixed-point format. The results show that the co-processing scheme operating at a conservative speed of 100 MHz can identify around 441 images per second, which is about 17% times faster than a 650 MHz - software implementation. It is difficult to compare our results against other implementations based on Field-Programmable Gate Array (FPGA), because the others implementations are not exactly like ours. However, some comparisons, regarding the logical resources used and accuracy, suggest that our work could be better than previous works.

Multiprocessor transport surveillance video system based on "system on chip" technology

2020 ◽  
Author(s):  
Ш.С. Фахми ◽  
Н.В. Шаталова ◽  
В.В. Вислогузов ◽  
Е.В. Костикова
Keyword(s):  
System On Chip ◽  
Reference Points ◽  
Surveillance Video ◽  
Video Information ◽  
Chip Technology ◽  
Intelligent Video Surveillance System ◽  
Speed Up ◽  
Algorithmic Analysis ◽  
Computational Procedures ◽  
On Chip

В данной работе предлагаются математический аппарат и архитектура многопроцессорной транспортной системы на кристалле (МПТСнК). Выполнена программно-аппаратная реализация интеллектуальной системы видеонаблюдения на базе технологии «система на кристалле» и с использованием аппаратного ускорителя известного метода формирования опорных векторов. Архитектура включает в себя сложно-функциональные блоки анализа видеоинформации на базе параллельных алгоритмов нахождения опорных точек изображений и множества элементарных процессоров для выполнения сложных вычислительных процедур алгоритмов анализа с использованием средств проектирования на базе реконфигурируемой системы на кристалле, позволяющей оценить количество аппаратных ресурсов. Предлагаемая архитектура МПТСнК позволяет ускорить обработку и анализ видеоинформации при решении задач обнаружения и распознавания чрезвычайных ситуаций и подозрительных поведений. In this paper, we propose the mathematical apparatus and architecture of a multiprocessor transport system on a chip (MPTSoC). Software and hardware implementation of an intelligent video surveillance system based on the "system on chip" technology and using a hardware accelerator of the well-known method of forming reference vectors. The architecture includes complex functional blocks for analyzing video information based on parallel algorithms for finding image reference points and a set of elementary processors for performing complex computational procedures for algorithmic analysis. using design tools based on a reconfigurable system on chip that allows you to estimate the amount of hardware resources. The proposed MPTSoC architecture makes it possible to speed up the processing and analysis of video information when solving problems of detecting and recognizing emergencies and suspicious behaviors

ОСОБЕННОСТИ АРХИТЕКТУРЫ И ОСНОВНЫЕ ХАРАКТЕРИСТИКИ АППАРАТНОГО ВИДЕОКОДЕКА СТАНДАРТА H.264 В СОСТАВЕ МИКРОСХЕМЫ 1892ВМ14Я

2020 ◽  
Vol 96 (3s) ◽  
pp. 89-96
Author(s):  
А.А. Беляев ◽  
Я.Я. Петричкович ◽  
Т.В. Солохина ◽  
И.А. Беляев
Keyword(s):  
Data Flow ◽  
System On Chip ◽  
Video Codec ◽  
Experimental Results ◽  
Video Sequences ◽  
Ip Core ◽  
Performance Measurements ◽  
Synchronization Mechanism ◽  
Architectural Features ◽  
On Chip

Рассмотрены особенности архитектуры и основные характеристики аппаратного видеокодека по стандарту H.264, входящего в состав микросхемы 1892ВМ14Я (MCom-02). Описан механизм синхронизации потоков данных на основе набора флагов событий. Приведены экспериментальные результаты измерения характеристик производительности разработанного видеокодека на реальных видеосюжетах при различных форматах передаваемого изображения. The paper considers main architectural features and characteristics of H.264 hardware video codec IP-core as a part of MCom- 02 system-on-chip (SoC). Bedides, it presents data flow synchronization mechanism based on event flags set, as well as experimental results of performance measurements for the designed video codec IP-core obtained for different video sequences and different image formats.

Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms

2020 ◽  
pp. 1-13
Author(s):  
Gokul Chandrasekaran ◽  
P.R. Karthikeyan ◽  
Neelam Sanjeev Kumar ◽  
Vanchinathan Kumarasamy
Keyword(s):  
Ant Colony Optimization ◽  
Artificial Bee Colony ◽  
Optimization Algorithms ◽  
System On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
Bee Colony ◽  
Ant Lion Optimization ◽  
Ant Lion ◽  
On Chip

Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.

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