scholarly journals A 130-NM CMOS 400 MHZ 8-Bit Low Power Binary Weighted Current Steering DAC

2016 ◽  
Vol 5 (4) ◽  
pp. 315-322
Author(s):  
Ashok Kumar Adepu ◽  
Kiran Kumar Kolupuri
Keyword(s):  
Low Power ◽  
Current Steering ◽  
Current Steering Dac ◽  
Binary Weighted

scholarly journals Design and implementation of 4 bit binary weighted current steering DAC

2020 ◽  
Vol 10 (6) ◽  
pp. 5642
Author(s):  
Jayeshkumar J. Patel ◽  
Amisha P. Naik
Keyword(s):  
Supply Voltage ◽  
Biomedical Application ◽  
Current Mode ◽  
Cmos Technology ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Transmission Gate ◽  
Linearity Error ◽  
Current Steering Dac ◽  
Binary Weighted

A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.

scholarly journals A 45 nm 6 Bit Low Power Current Steering Digital to Analog Converter Using GDI Logic

2015 ◽  
Vol 16 (1) ◽  
pp. 46
Author(s):  
Bharat H. Nagpara
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Transient Analysis ◽  
Average Power ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Design And Implementation ◽  
Analog Converter ◽  
Digital To Analog ◽  
Current Steering Dac

<p><strong><em> </em></strong>In this paper, The Design and Implementation low power Current Steering Digital to Analog Converter in 45 nm technology using GDI Logic using TANNER TOOL, V15 is presented. This architecture gives the most optimized results in terms of speed, resolution and power. The designed 6-bit DAC operates with two supply voltages, 1 V and 3.3 V. The simulation result shows the transient analysis waveforms of current Steering DAC. The average power dissipation is 364.06 μW. The tool used for simulation is Tanner S-Edit and T-Spice. Comparisons show that using GDI logic, it consists low power as compare to the CMOS logic.</p>

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