An Iterative Data-Flow Optimal Scheduling Algorithm based on Genetic Algorithm for High-Performance Multiprocessor

2015 ◽  
Vol 15 (6) ◽  
pp. 115-121
Author(s):  
Jeong-Uk Chang ◽  
◽  
Chi-Ho Lim
Keyword(s):  
Genetic Algorithm ◽  
High Performance ◽  
Data Flow ◽  
Scheduling Algorithm ◽  
Optimal Scheduling

Task scheduling algorithm based on improved genetic algorithm in cloud computing environment

2020 ◽  
Vol 13 ◽  
Author(s):  
Ge Weiqing ◽  
Cui Yanru
Keyword(s):  
Genetic Algorithm ◽  
Cloud Computing ◽  
Task Scheduling ◽  
Scheduling Algorithm ◽  
Task Completion ◽  
Improved Genetic Algorithm ◽  
Fitness Functions ◽  
Task Scheduling Algorithm ◽  
Simulation Results

Background: In order to make up for the shortcomings of the traditional algorithm, Min-Min and Max-Min algorithm are combined on the basis of the traditional genetic algorithm. Methods: In this paper, a new cloud computing task scheduling algorithm is proposed, which introduces Min-Min and Max-Min algorithm to generate initialization population, and selects task completion time and load balancing as double fitness functions, which improves the quality of initialization population, algorithm search ability and convergence speed. Results: The simulation results show that the algorithm is superior to the traditional genetic algorithm and is an effective cloud computing task scheduling algorithm. Conclusion: Finally, this paper proposes the possibility of the fusion of the two quadratively improved algorithms and completes the preliminary fusion of the algorithm, but the simulation results of the new algorithm are not ideal and need to be further studied.

scholarly journals An Adaptive Throughput-First Packet Scheduling Algorithm for DPDK-Based Packet Processing Systems

2021 ◽  
Vol 13 (3) ◽  
pp. 78
Author(s):  
Chuanhong Li ◽  
Lei Song ◽  
Xuewen Zeng
Keyword(s):  
Packet Loss ◽  
High Performance ◽  
Packet Scheduling ◽  
Scheduling Algorithm ◽  
Processing System ◽  
System Throughput ◽  
Packet Processing ◽  
Research Attention ◽  
Continuous Increase ◽  
Packet Scheduling Algorithm

The continuous increase in network traffic has sharply increased the demand for high-performance packet processing systems. For a high-performance packet processing system based on multi-core processors, the packet scheduling algorithm is critical because of the significant role it plays in load distribution, which is related to system throughput, attracting intensive research attention. However, it is not an easy task since the canonical flow-level packet scheduling algorithm is vulnerable to traffic locality, while the packet-level packet scheduling algorithm fails to maintain cache affinity. In this paper, we propose an adaptive throughput-first packet scheduling algorithm for DPDK-based packet processing systems. Combined with the feature of DPDK burst-oriented packet receiving and transmitting, we propose using Subflow as the scheduling unit and the adjustment unit making the proposed algorithm not only maintain the advantages of flow-level packet scheduling algorithms when the adjustment does not happen but also avoid packet loss as much as possible when the target core may be overloaded Experimental results show that the proposed method outperforms Round-Robin, HRW (High Random Weight), and CRC32 on system throughput and packet loss rate.

scholarly journals High-Performance Parallel Implementation of Genetic Algorithm on FPGA

2019 ◽  
Vol 38 (9) ◽  
pp. 4014-4039 ◽  
Author(s):  
Matheus F. Torquato ◽  
Marcelo A. C. Fernandes
Keyword(s):  
Genetic Algorithm ◽  
High Performance ◽  
Parallel Implementation

A High-Performance Scheduling Algorithm Based on Packet Sto

2005 ◽  
Author(s):  
Jing Qu ◽  
Ximing Hu ◽  
Peng Yi ◽  
Xingming Zhang ◽  
Binqiang Wang
Keyword(s):  
High Performance ◽  
Scheduling Algorithm

scholarly journals Fault Tolerant PLBGSA: Precedence Level Based Genetic Scheduling Algorithm for P2P Grid

2013 ◽  
Vol 2013 ◽  
pp. 1-13 ◽  
Author(s):  
Piyush Chauhan ◽  
Nitin
Keyword(s):  
Genetic Algorithm ◽  
Directed Acyclic Graph ◽  
Fault Tolerant ◽  
Scheduling Algorithm ◽  
Complex Task ◽  
Grid Scheduling ◽  
Complex Tasks ◽  
Small Organizations ◽  
Grid Resources ◽  
Desirable Trait

Due to monetary limitation, small organizations cannot afford high end supercomputers to solve highly complex tasks. P2P (peer to peer) grid computing is being used nowadays to break complex task into subtasks in order to solve them on different grid resources. Workflows are used to represent these complex tasks. Finishing such complex task in a P2P grid requires scheduling subtasks of workflow in an optimized manner. Several factors play their part in scheduling decisions. The genetic algorithm is very useful in scheduling DAG (directed acyclic graph) based task. Benefit of a genetic algorithm is that it takes into consideration multiple criteria while scheduling. In this paper, we have proposed a precedence level based genetic algorithm (PLBGSA), which yields schedules for workflows in a decentralized fashion. PLBGSA is compared with existing genetic algorithm based scheduling techniques. Fault tolerance is a desirable trait of a P2P grid scheduling algorithm due to the untrustworthy nature of grid resources. PLBGSA handles faults efficiently.

Lane Detection Algorithm Based on Genetic Algorithm and its Parallel Computing Realization

2012 ◽  
Vol 479-481 ◽  
pp. 65-70
Author(s):  
Xiao Hui Zhang ◽  
Liu Qing ◽  
Mu Li
Keyword(s):  
Genetic Algorithm ◽  
Data Transmission ◽  
High Speed ◽  
High Performance ◽  
Large Data ◽  
Detection Algorithm ◽  
Lane Detection ◽  
The Road ◽  
Time Problem ◽  
High Speed Data

Based on the target detection of alignment template, the paper designs a lane alignment template by using correlation matching method, and combines with genetic algorithm for template stochastic matching and optimization to realize the lane detection. In order to solve the real-time problem of lane detection algorithm based on genetic algorithm, this paper uses the high performance multi-core DSP chip TMS320C6474 as the core, combines with high-speed data transmission technology of Rapid10, realizes the hardware parallel processing of the lane detection algorithm. By Rapid10 bus, the data transmission speed between the DSP and the DSP can reach 3.125Gbps, it basically realizes transmission without delay, and thereby solves the high speed transmission of the large data quantity between processor. The experimental results show that, no matter the calculated lane line, or the running time is better than the single DSP and PC at the parallel C6474 platform. In addition, the road detection is accurate and reliable, and it has good robustness.

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