Lane Detection Algorithm Based on Genetic Algorithm and its Parallel Computing Realization

2012 ◽  
Vol 479-481 ◽  
pp. 65-70
Author(s):  
Xiao Hui Zhang ◽  
Liu Qing ◽  
Mu Li
Keyword(s):  
Genetic Algorithm ◽  
Data Transmission ◽  
High Speed ◽  
High Performance ◽  
Large Data ◽  
Detection Algorithm ◽  
Lane Detection ◽  
The Road ◽  
Time Problem ◽  
High Speed Data

Based on the target detection of alignment template, the paper designs a lane alignment template by using correlation matching method, and combines with genetic algorithm for template stochastic matching and optimization to realize the lane detection. In order to solve the real-time problem of lane detection algorithm based on genetic algorithm, this paper uses the high performance multi-core DSP chip TMS320C6474 as the core, combines with high-speed data transmission technology of Rapid10, realizes the hardware parallel processing of the lane detection algorithm. By Rapid10 bus, the data transmission speed between the DSP and the DSP can reach 3.125Gbps, it basically realizes transmission without delay, and thereby solves the high speed transmission of the large data quantity between processor. The experimental results show that, no matter the calculated lane line, or the running time is better than the single DSP and PC at the parallel C6474 platform. In addition, the road detection is accurate and reliable, and it has good robustness.

High-Speed Data Transmissions Using Tomlinson-Harashima Precoding

2013 ◽  
Vol 596 ◽  
pp. 199-203 ◽  
Author(s):  
Yosuke Iijima ◽  
Yasushi Yuminaka
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
High Performance ◽  
Average Power ◽  
Pulse Amplitude ◽  
Coaxial Cable ◽  
Experimental Implementation ◽  
Low Pass ◽  
High Speed Data ◽  
Speed Data Transmission

High-speed interfaces become an important role to achieve high performance VLSIsystems. This paper demonstrates a high-speed data transmission technique using Tomlinson-Harashima Precoding (THP). The THP can compensate for low-pass effect of an interconnec-tion at a transmitter, and it can also limit peak and average power of a transmitted signal. Inthis paper, a 200Mbps 4-PAM(Pulse-amplitude modulation) transmitter is designed and simu-lated to demonstrate the THP performance. The experimental implementation using an FPGAdemonstrates high-speed transmission over a long 3D2V coaxial cable.

Design and Implementation of Serial RapidIO Based on DSP and FPGA

2014 ◽  
Vol 971-973 ◽  
pp. 1581-1585 ◽  
Author(s):  
Jun Liu ◽  
Yan Tian ◽  
Wei Hao ◽  
Lei Qu
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
High Performance ◽  
Data Exchange ◽  
Performance Testing ◽  
Transfer Data ◽  
Design And Implementation ◽  
High Speed Data ◽  
Data Transmission System ◽  
Interface Protocol

In order to meet the request of high-speed data exchange in embedded systems, this paper details the high-speed SRIO (Serial RapidIO) interface protocol and the process of SRIO access timing between the local endpoint devices and the remote endpoint devices. And also we implement the design of the new high-performance RapidIO interconnection between DSP and FPGA. Through the performance testing of SRIO data transmission system, experimental results show that the design can stably transfer data at high speed between processors.

The Study of the PCI Bus Expansion Based on PCI Bridge Chip

2013 ◽  
Vol 760-762 ◽  
pp. 1695-1698
Author(s):  
Jin Xu ◽  
Jing Guo ◽  
Zheng Mao Mei
Keyword(s):  
Circuit Design ◽  
Data Transmission ◽  
High Speed ◽  
High Performance ◽  
Pci Bus ◽  
Depth Analysis ◽  
Peripheral Component Interconnect ◽  
High Speed Data ◽  
Bridge Technology ◽  
Speed Data Transmission

PCI (Peripheral Component Interconnect) bus is a high-performance local bus, is put forward to meet the high-speed data transmission between peripherals and host. The CPCI technology is adapted from PCI-based, it conforms to the PCI bus standard and mature European card mechanical standards , supports hot-swap capability, has advantage of the more stronger, more reliable, use and maintenance simply. Can break through the limitations of the PCI card via the PCI bridge technology to achieve PCI to CPCI conversion, the paper introduces the principle of the PCI-PCI bridge technology and in-depth analysis of a typical bridge chip PCI2050, based on a PCI card circuit design example, and provide a reference for the type of system design and verification.

Analysis of Inter-Satellite Optical Wireless Communication System

2017 ◽  
Vol 7 (10) ◽  
pp. 10
Author(s):  
Rajbir Singh
Keyword(s):  
Wireless Communication ◽  
Optical Networks ◽  
Data Transmission ◽  
High Speed ◽  
Open Space ◽  
Communication Link ◽  
Optical Wireless Communication ◽  
Optical Wireless ◽  
High Speed Data ◽  
Speed Data Transmission

Optical networks are bandwidth efficient networks are used for long haul communication providing seamless data transfer. For high speed data transmission in open space between different satellites, Inter-satellite Optical wireless communication (IsOWC) is widely used .In this paper we have evaluated the performance of IsOWC communication link for high speed data transmission .The performance of the system is evaluated on the basis of qualitative parameters such as Q-factor and BER using optisystem simulator.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

Top-down Fabricated Gold Nanostrip on Silicon-on-insulator Wafer: A Promising Building Block towards Ultra-compact Optical Device

Nanoscale ◽  
2020 ◽  
Author(s):  
Fuping Zhang ◽  
Weikang Liu ◽  
Li Chen ◽  
Zhiqiang Guan ◽  
Hongxing Xu
Keyword(s):  
Optical Communication ◽  
Data Transmission ◽  
Building Block ◽  
High Speed ◽  
Large Data ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Fundamental Building Block ◽  
Low Energy Consumption ◽  
Controllable Fabrication

he plasmonic waveguide is the fundamental building block for high speed, large data transmission capacity, low energy consumption optical communication and sensing. Controllable fabrication and simultaneously optimization of the propagation...

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